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Create PCI Command Register kernel defines, replace PCNet identical defines with new global defines.

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TomAwezome 2022-12-30 17:45:58 -05:00
parent 0f1a63f0a2
commit 64703e9a12
2 changed files with 13 additions and 8 deletions
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10
src/Home/Net/Drivers/PCNet.ZC
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@ -1,5 +1,5 @@
/* AMD PCNetII Driver /* AMD PCNetII Driver
Author: TomAwezome Authors: ($TX,"minexew",HTML="https://github.com/minexew/"$), $TX,"TomAwezome",HTML="https://github.com/TomAwezome/"$, $TX,"TheTinkerer",HTML="https://github.com/tinkeros/"$
Driver is based on: Driver is based on:
- minexew's ShrineOS PCNet implementation - minexew's ShrineOS PCNet implementation
@ -13,12 +13,6 @@
- Clear documentation. - Clear documentation.
*/ */
#define PCNET_CMDf_IOEN 0
#define PCNET_CMDf_BMEN 2
#define PCNET_CMDF_IOEN (1 << PCNET_CMDf_IOEN)
#define PCNET_CMDF_BMEN (1 << PCNET_CMDf_BMEN)
#define PCNET_WD_RESET 0x14 // reset reg location when card is in 16-bit mode #define PCNET_WD_RESET 0x14 // reset reg location when card is in 16-bit mode
#define PCNET_DW_RDP 0x10 #define PCNET_DW_RDP 0x10
@ -704,7 +698,7 @@ U0 PCNetInit()
pcnet.pci->dev, pcnet.pci->dev,
pcnet.pci->fun, pcnet.pci->fun,
PCIR_COMMAND, PCIR_COMMAND,
PCNET_CMDF_IOEN | PCNET_CMDF_BMEN); PCI_CMDF_IOEN | PCI_CMDF_BMEN);
PCNetReset; PCNetReset;

11
src/Kernel/KernelA.HH
View file

@ -2658,6 +2658,17 @@ class CSMBIOSBatteryInfo
#define PCIR_MIN_GRANT 0x3E #define PCIR_MIN_GRANT 0x3E
#define PCIR_MAX_LATENCY 0x3F #define PCIR_MAX_LATENCY 0x3F
// PCI Command Register bit flags
#define PCI_CMDf_IOEN 0 // I/O Space Enable
#define PCI_CMDf_MSEN 1 // Memory Space Enable
#define PCI_CMDf_BMEN 2 // Bus Master Enable
#define PCI_CMDf_INTD 10 // Interrupt Disable
#define PCI_CMDF_IOEN (1 << PCI_CMDf_IOEN)
#define PCI_CMDF_MSEN (1 << PCI_CMDf_MSEN)
#define PCI_CMDF_BMEN (1 << PCI_CMDf_BMEN)
#define PCI_CMDF_INTD (1 << PCI_CMDf_INTD)
//PCI class codes //PCI class codes
#define PCIC_STORAGE 0x1 #define PCIC_STORAGE 0x1
#define PCIC_NETWORK 0x2 #define PCIC_NETWORK 0x2