From 64703e9a120a6d35dc0b254e8b556863a3944c2e Mon Sep 17 00:00:00 2001
From: TomAwezome <sonidd1@yahoo.com>
Date: Fri, 30 Dec 2022 17:45:58 -0500
Subject: [PATCH] Create PCI Command Register kernel defines, replace PCNet
 identical defines with new global defines.

---
 src/Home/Net/Drivers/PCNet.ZC | 10 ++--------
 src/Kernel/KernelA.HH         | 11 +++++++++++
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/Home/Net/Drivers/PCNet.ZC b/src/Home/Net/Drivers/PCNet.ZC
index 26b09f1d..5c454aa9 100644
--- a/src/Home/Net/Drivers/PCNet.ZC
+++ b/src/Home/Net/Drivers/PCNet.ZC
@@ -1,5 +1,5 @@
 /*	AMD PCNetII Driver
-	Author: TomAwezome
+	Authors: ($TX,"minexew",HTML="https://github.com/minexew/"$), $TX,"TomAwezome",HTML="https://github.com/TomAwezome/"$, $TX,"TheTinkerer",HTML="https://github.com/tinkeros/"$
 
 	Driver is based on:
 	-	minexew's ShrineOS PCNet implementation
@@ -13,12 +13,6 @@
 	-	Clear documentation.
 */
 
-#define	PCNET_CMDf_IOEN	0
-#define	PCNET_CMDf_BMEN	2
-
-#define PCNET_CMDF_IOEN	(1 << PCNET_CMDf_IOEN)
-#define PCNET_CMDF_BMEN	(1 << PCNET_CMDf_BMEN)
-
 #define PCNET_WD_RESET	0x14 // reset reg location when card is in 16-bit mode
 
 #define PCNET_DW_RDP	0x10
@@ -704,7 +698,7 @@ U0 PCNetInit()
 				pcnet.pci->dev,
 				pcnet.pci->fun,
 				PCIR_COMMAND,
-				PCNET_CMDF_IOEN | PCNET_CMDF_BMEN);
+				PCI_CMDF_IOEN | PCI_CMDF_BMEN);
 
 	PCNetReset;
 
diff --git a/src/Kernel/KernelA.HH b/src/Kernel/KernelA.HH
index eafb7fcc..4a9046b8 100755
--- a/src/Kernel/KernelA.HH
+++ b/src/Kernel/KernelA.HH
@@ -2658,6 +2658,17 @@ class CSMBIOSBatteryInfo
 #define PCIR_MIN_GRANT			0x3E
 #define PCIR_MAX_LATENCY		0x3F
 
+// PCI Command Register bit flags
+#define	PCI_CMDf_IOEN	0	// I/O Space Enable
+#define	PCI_CMDf_MSEN	1	// Memory Space Enable
+#define	PCI_CMDf_BMEN	2	// Bus Master Enable
+#define PCI_CMDf_INTD	10	// Interrupt Disable
+
+#define PCI_CMDF_IOEN	(1 << PCI_CMDf_IOEN)
+#define	PCI_CMDF_MSEN	(1 << PCI_CMDf_MSEN)
+#define PCI_CMDF_BMEN	(1 << PCI_CMDf_BMEN)
+#define PCI_CMDF_INTD	(1 << PCI_CMDf_INTD)
+
 //PCI class codes
 #define PCIC_STORAGE	0x1
 #define PCIC_NETWORK	0x2