28 lines
548 B
Makefile
28 lines
548 B
Makefile
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# Define the compiler and flags
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CC = gcc
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CFLAGS = -Wall -Wextra -Werror
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# Define the target executable and the source files
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TARGET = caur
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SRCS = $(wildcard src/*.c)
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OBJS = $(SRCS:.c=.o)
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# The default rule: build the target
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all: $(TARGET)
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# Link the object files into the target executable
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$(TARGET): $(OBJS)
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$(CC) $(CFLAGS) -o $(TARGET) $(OBJS)
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# Compile the .c files into .o files
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%.o: %.c
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$(CC) $(CFLAGS) -c $< -o $@
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# Clean up the build artifacts
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clean:
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rm -f $(TARGET) $(OBJS)
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# Run the program
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run: $(TARGET)
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./$(TARGET)
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