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89 lines
2.9 KiB
Text
Executable file
89 lines
2.9 KiB
Text
Executable file
$WW,1$$FG,5$$TX+CX,"64-Bit Assembly Quiz"$$FG$
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1) In 64-bit mode, how many bytes are always pushed?
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PUSH 12
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PUSH EAX
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2) What happens to the upper 32-bits?
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XOR EAX,EAX
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MOV EAX,0x12345678
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MOV EAX,0x80000000
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3) How do you set FS or GS values?
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4) If FS points to current task record, what's wrong with this instruction?
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MOV RAX,U64 FS:[TSS_SOME_MEMBER]
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5) Which instruction takes more bytes?
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MOV RAX,U64 [R8]
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MOV RAX,U64 [R13]
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6) Are these the same number of bytes?
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MOV RAX,1234
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MOV R8,1234
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MOV EAX,1234
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7) True or False
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a) You can access the lowest byte of RAX.
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b) You can access the lowest byte of ESI.
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c) You can access the second-to-lowest byte of RAX.
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d) You can access the second-to-lowest byte of ESI.
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8) How do you call a subroutine at 0x10,0000,0000 from code at 0x00,0010,0000?
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9) How much faster is a REL32 call instruction compared to a software interrupt or SYSCALL?
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10) How long does an IN or OUT instruction take on a 1GHz machine and on a 3GHz machine?
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11) How do you push all 16 regs?
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12) Should you put the regs in a TSS?
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13) You can have 4K or 4Meg pages in 32-bit mode. You can have 4K or what size pages in 64-bit mode?
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14) On a fresh CPU with an empty TLB, how many memory accesses (page tables) does it take to access one virtual address?
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----
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TempleOS identity-maps everything, all the time, so the usual convention of upper memory being for kernel does not apply. It uses physical addresses, basically. It puts all code in the lowest 2-Gig memory range so that it can use the CALL REL32 instruction, the fastest. It never changes privilege levels or messes with page tables, once it is up-and-running.
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----
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ANSWERS:
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1) All stack pushes and pops are 64-bits.
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2) The upper 32-bits are set to zero.
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3) To set FS or GS, you use WRMSR to write a model specific reg. See $LK,"IA32_FS_BASE",A="MN:IA32_FS_BASE"$ and $LK,"SET_FS_BASE",A="MN:SET_FS_BASE"$.
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4) Displacement addressing is now RIP relative, so RIP would be added to TSS_SOME_MEMBER. (Useless)
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5) The R13 instruction takes one more byte because it is like $LK,"REG_RBP",A="MN:REG_RBP"$ in the ModR.
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6) The R8 instruction needs a REX byte prefix to specify upper-8 reg.
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7) You can access the lowest byte of any reg. You can access AH but not the second-to-lowest byte of ESI.
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8) To call a subroutine farther than 2Gig away, you put the address into RAX, then CALL RAX.
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9) CALL REL32 is significantly faster. See $LK,"::/Demo/Lectures/InterruptDemo.HC"$.
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10) IN or OUT instructions happen at a fixed speed based on the original ISA bus clock.
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11) PUSHAD is not available for 64-bit mode, so you do it by hand.
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12) The TSS is no longer used to hold the task state because there are 16 regs and they are 64-bits, not 32-bits. I guess Intel decided doing it by hand was better than TSSes.
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13) 64-bit mode has 4K or 2Meg page size.
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14) For one access, there are 3-4 levels of page tables plus the location itself.
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