mirror of
https://github.com/Zeal-Operating-System/ZealOS.git
synced 2024-12-29 00:36:32 +00:00
dbf8647d59
Added top & right borders to RawDr. Improved spacing in some debug and compiler reporting. Fixed RawPutChar and EdLite tab width. Fixed Ui missing '0x' prefix syntax highlighter bug. Added 32BitPaint demo.
1339 lines
54 KiB
HTML
Executable file
1339 lines
54 KiB
HTML
Executable file
<!DOCTYPE HTML>
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<html>
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<head>
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<meta http-equiv="Content-Type" content="text/html;charset=US-ASCII">
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<meta name="generator" content="ZealOS V0.08">
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<style type="text/css">
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body {background-color:#000000;}
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.cF0{color:#ffffff;background-color:#000000;}
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.cF1{color:#3465a4;background-color:#000000;}
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.cF2{color:#4e9a06;background-color:#000000;}
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.cF3{color:#06989a;background-color:#000000;}
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.cF4{color:#a24444;background-color:#000000;}
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.cF5{color:#75507b;background-color:#000000;}
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.cF6{color:#ce982f;background-color:#000000;}
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.cF7{color:#bcc0b9;background-color:#000000;}
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.cF8{color:#555753;background-color:#000000;}
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.cF9{color:#729fcf;background-color:#000000;}
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.cFA{color:#82bc49;background-color:#000000;}
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.cFB{color:#34e2e2;background-color:#000000;}
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.cFC{color:#ac3535;background-color:#000000;}
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.cFD{color:#ad7fa8;background-color:#000000;}
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.cFE{color:#fce94f;background-color:#000000;}
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.cFF{color:#000000;background-color:#000000;}
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</style>
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</head>
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<body>
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<pre style="font-family:monospace;font-size:12pt">
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<a name="l1"></a><span class=cF0>/* See </span><a href="https://tomawezome.github.io/ZealOS/Compiler/AsmInit.CC.html#l61"><span class=cF4>AsmHashLoad</span></a><span class=cF0>().
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<a name="l2"></a>
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<a name="l3"></a>'!'= IEF_DONT_SWITCH_MODES
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<a name="l4"></a>'&'= IEF_DEFAULT
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<a name="l5"></a>'%'= IEF_NOT_IN_64_BIT Not Allowed in 64-bit.
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<a name="l6"></a>'='= IEF_48_REX Rex 0x48 only if in 64-bit mode.
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<a name="l7"></a>'`'= IEF_REX_ONLY_R8_R15
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<a name="l8"></a>'^'= IEF_REX_XOR_LIKE
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<a name="l9"></a>'*'= IEF_STI_LIKE Floating STI-like for UAsm.
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<a name="l10"></a>'$'= IEF_ENDING_ZERO Ending zero for ENTER.
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<a name="l11"></a>
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<a name="l12"></a></span><span class=cF4>Note:</span><span class=cF0> ZealOS uses nonstandard opcodes.
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<a name="l13"></a>Asm is kind-of a bonus and Terry made changes
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<a name="l14"></a>to make the assembler simpler. For opcodes
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<a name="l15"></a>which can have different numbers of
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<a name="l16"></a>args, he separated them out -- Like IMUL and IMUL2.
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<a name="l17"></a>The assembler will not report certain invalid
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<a name="l18"></a>forms. Get an Intel datasheet and learn
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<a name="l19"></a>which forms are valid.
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<a name="l20"></a>
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<a name="l21"></a>{Lock|Rep}{Seg|2E=NotBr|3E=Br}{OP}{ADD}{REX}
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<a name="l22"></a>
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<a name="l23"></a>':' is start of alias list. Marked with OCF_ALIAS.
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<a name="l24"></a>*/
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<a name="l25"></a>
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<a name="l26"></a>R8 AL 0;
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<a name="l27"></a>R8 CL 1;
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<a name="l28"></a>R8 DL 2;
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<a name="l29"></a>R8 BL 3;
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<a name="l30"></a>R8 AH 4;
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<a name="l31"></a>R8 CH 5;
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<a name="l32"></a>R8 DH 6;
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<a name="l33"></a>R8 BH 7;
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<a name="l34"></a>R8 R8u8 8;
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<a name="l35"></a>R8 R9u8 9;
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<a name="l36"></a>R8 R10u8 10;
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<a name="l37"></a>R8 R11u8 11;
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<a name="l38"></a>R8 R12u8 12;
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<a name="l39"></a>R8 R13u8 13;
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<a name="l40"></a>R8 R14u8 14;
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<a name="l41"></a>R8 R15u8 15;
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<a name="l42"></a>R8 RSPu8 20;
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<a name="l43"></a>R8 RBPu8 21;
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<a name="l44"></a>R8 RSIu8 22;
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<a name="l45"></a>R8 RDIu8 23;
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<a name="l46"></a>
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<a name="l47"></a>R16 AX 0;
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<a name="l48"></a>R16 CX 1;
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<a name="l49"></a>R16 DX 2;
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<a name="l50"></a>R16 BX 3;
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<a name="l51"></a>R16 SP 4;
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<a name="l52"></a>R16 BP 5;
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<a name="l53"></a>R16 SI 6;
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<a name="l54"></a>R16 DI 7;
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<a name="l55"></a>R16 R8u16 8;
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<a name="l56"></a>R16 R9u16 9;
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<a name="l57"></a>R16 R10u16 10;
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<a name="l58"></a>R16 R11u16 11;
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<a name="l59"></a>R16 R12u16 12;
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<a name="l60"></a>R16 R13u16 13;
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<a name="l61"></a>R16 R14u16 14;
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<a name="l62"></a>R16 R15u16 15;
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<a name="l63"></a>
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<a name="l64"></a>R32 EAX 0;
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<a name="l65"></a>R32 ECX 1;
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<a name="l66"></a>R32 EDX 2;
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<a name="l67"></a>R32 EBX 3;
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<a name="l68"></a>R32 ESP 4;
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<a name="l69"></a>R32 EBP 5;
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<a name="l70"></a>R32 ESI 6;
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<a name="l71"></a>R32 EDI 7;
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<a name="l72"></a>R32 R8u32 8;
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<a name="l73"></a>R32 R9u32 9;
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<a name="l74"></a>R32 R10u32 10;
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<a name="l75"></a>R32 R11u32 11;
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<a name="l76"></a>R32 R12u32 12;
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<a name="l77"></a>R32 R13u32 13;
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<a name="l78"></a>R32 R14u32 14;
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<a name="l79"></a>R32 R15u32 15;
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<a name="l80"></a>
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<a name="l81"></a>R64 RAX 0;
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<a name="l82"></a>R64 RCX 1;
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<a name="l83"></a>R64 RDX 2;
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<a name="l84"></a>R64 RBX 3;
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<a name="l85"></a>R64 RSP 4;
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<a name="l86"></a>R64 RBP 5;
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<a name="l87"></a>R64 RSI 6;
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<a name="l88"></a>R64 RDI 7;
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<a name="l89"></a>R64 R8 8;
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<a name="l90"></a>R64 R9 9;
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<a name="l91"></a>R64 R10 10;
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<a name="l92"></a>R64 R11 11;
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<a name="l93"></a>R64 R12 12;
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<a name="l94"></a>R64 R13 13;
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<a name="l95"></a>R64 R14 14;
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<a name="l96"></a>R64 R15 15;
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<a name="l97"></a>R64 R8u64 8;
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<a name="l98"></a>R64 R9u64 9;
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<a name="l99"></a>R64 R10u64 10;
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<a name="l100"></a>R64 R11u64 11;
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<a name="l101"></a>R64 R12u64 12;
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<a name="l102"></a>R64 R13u64 13;
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<a name="l103"></a>R64 R14u64 14;
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<a name="l104"></a>R64 R15u64 15;
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<a name="l105"></a>
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<a name="l106"></a>SEG ES 0;
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<a name="l107"></a>SEG CS 1;
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<a name="l108"></a>SEG SS 2;
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<a name="l109"></a>SEG DS 3;
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<a name="l110"></a>SEG FS 4;
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<a name="l111"></a>SEG GS 5;
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<a name="l112"></a>
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<a name="l113"></a>FSTACK ST0 0;
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<a name="l114"></a>FSTACK ST1 1;
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<a name="l115"></a>FSTACK ST2 2;
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<a name="l116"></a>FSTACK ST3 3;
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<a name="l117"></a>FSTACK ST4 4;
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<a name="l118"></a>FSTACK ST5 5;
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<a name="l119"></a>FSTACK ST6 6;
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<a name="l120"></a>FSTACK ST7 7;
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<a name="l121"></a>
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<a name="l122"></a>MM MM0 0;
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<a name="l123"></a>MM MM1 1;
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<a name="l124"></a>MM MM2 2;
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<a name="l125"></a>MM MM3 3;
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<a name="l126"></a>MM MM4 4;
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<a name="l127"></a>MM MM5 5;
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<a name="l128"></a>MM MM6 6;
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<a name="l129"></a>MM MM7 7;
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<a name="l130"></a>
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<a name="l131"></a>XMM XMM0 0;
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<a name="l132"></a>XMM XMM1 1;
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<a name="l133"></a>XMM XMM2 2;
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<a name="l134"></a>XMM XMM3 3;
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<a name="l135"></a>XMM XMM4 4;
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<a name="l136"></a>XMM XMM5 5;
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<a name="l137"></a>XMM XMM6 6;
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<a name="l138"></a>XMM XMM8 8;
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<a name="l139"></a>XMM XMM9 9;
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<a name="l140"></a>XMM XMM10 10;
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<a name="l141"></a>XMM XMM11 11;
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<a name="l142"></a>XMM XMM12 12;
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<a name="l143"></a>XMM XMM13 13;
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<a name="l144"></a>XMM XMM14 14;
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<a name="l145"></a>XMM XMM15 15;
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<a name="l146"></a>
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<a name="l147"></a>KEYWORD include 0;
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<a name="l148"></a>KEYWORD define 1;
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<a name="l149"></a>KEYWORD union 2;
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<a name="l150"></a>KEYWORD catch 3;
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<a name="l151"></a>KEYWORD class 4;
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<a name="l152"></a>KEYWORD try 5;
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<a name="l153"></a>KEYWORD if 6;
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<a name="l154"></a>KEYWORD else 7;
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<a name="l155"></a>KEYWORD for 8;
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<a name="l156"></a>KEYWORD while 9;
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<a name="l157"></a>KEYWORD extern 10;
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<a name="l158"></a>KEYWORD _extern 11;
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<a name="l159"></a>KEYWORD return 12;
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<a name="l160"></a>KEYWORD sizeof 13;
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<a name="l161"></a>KEYWORD _intern 14;
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<a name="l162"></a>KEYWORD do 15;
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<a name="l163"></a>KEYWORD asm 16;
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<a name="l164"></a>KEYWORD goto 17;
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<a name="l165"></a>KEYWORD exe 18;
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<a name="l166"></a>KEYWORD break 19;
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<a name="l167"></a>KEYWORD switch 20;
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<a name="l168"></a>KEYWORD start 21;
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<a name="l169"></a>KEYWORD end 22;
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<a name="l170"></a>KEYWORD case 23;
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<a name="l171"></a>KEYWORD default 24;
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<a name="l172"></a>KEYWORD public 25;
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<a name="l173"></a>KEYWORD offset 26;
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<a name="l174"></a>KEYWORD import 27;
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<a name="l175"></a>KEYWORD _import 28;
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<a name="l176"></a>KEYWORD ifdef 29;
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<a name="l177"></a>KEYWORD ifndef 30;
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<a name="l178"></a>KEYWORD ifaot 31;
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<a name="l179"></a>KEYWORD ifjit 32;
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<a name="l180"></a>KEYWORD endif 33;
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<a name="l181"></a>KEYWORD assert 34;
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<a name="l182"></a>KEYWORD reg 35;
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<a name="l183"></a>KEYWORD noreg 36;
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<a name="l184"></a>KEYWORD lastclass 37;
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<a name="l185"></a>KEYWORD no_warn 38;
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<a name="l186"></a>KEYWORD help_index 39;
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<a name="l187"></a>KEYWORD help_file 40;
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<a name="l188"></a>KEYWORD static 41;
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<a name="l189"></a>KEYWORD lock 42;
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<a name="l190"></a>KEYWORD defined 43;
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<a name="l191"></a>KEYWORD interrupt 44;
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<a name="l192"></a>KEYWORD haserrcode 45;
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<a name="l193"></a>KEYWORD argpop 46;
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<a name="l194"></a>KEYWORD noargpop 47;
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<a name="l195"></a>
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<a name="l196"></a>ASM_KEYWORD ALIGN 64;
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<a name="l197"></a>ASM_KEYWORD ORG 65;
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<a name="l198"></a>ASM_KEYWORD I0 66;
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<a name="l199"></a>ASM_KEYWORD I8 67;
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<a name="l200"></a>ASM_KEYWORD I16 68;
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<a name="l201"></a>ASM_KEYWORD I32 69;
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<a name="l202"></a>ASM_KEYWORD I64 70;
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<a name="l203"></a>ASM_KEYWORD U0 71;
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<a name="l204"></a>ASM_KEYWORD U8 72;
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<a name="l205"></a>ASM_KEYWORD U16 73;
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<a name="l206"></a>ASM_KEYWORD U32 74;
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<a name="l207"></a>ASM_KEYWORD U64 75;
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<a name="l208"></a>ASM_KEYWORD F64 76;
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<a name="l209"></a>ASM_KEYWORD DU8 77;
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<a name="l210"></a>ASM_KEYWORD DU16 78;
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<a name="l211"></a>ASM_KEYWORD DU32 79;
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<a name="l212"></a>ASM_KEYWORD DU64 80;
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<a name="l213"></a>ASM_KEYWORD DUP 81;
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<a name="l214"></a>ASM_KEYWORD USE16 82;
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<a name="l215"></a>ASM_KEYWORD USE32 83;
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<a name="l216"></a>ASM_KEYWORD USE64 84;
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<a name="l217"></a>ASM_KEYWORD IMPORT 85;
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<a name="l218"></a>ASM_KEYWORD LIST 86;
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<a name="l219"></a>ASM_KEYWORD NOLIST 87;
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<a name="l220"></a>ASM_KEYWORD BINFILE 88;
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<a name="l221"></a>
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<a name="l222"></a>OPCODE PUSH
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<a name="l223"></a> 0x0E, CS
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<a name="l224"></a> 0x16, SS
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<a name="l225"></a> 0x1E, DS
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<a name="l226"></a> 0x06, ES
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<a name="l227"></a> 0x0F 0xA0, FS
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<a name="l228"></a> 0x0F 0xA8, GS
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<a name="l229"></a> 0x6A, &IB IMM8
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<a name="l230"></a> 0x68, 16 !IW IMM16
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<a name="l231"></a> 0x68, 32 !ID IMM32
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<a name="l232"></a> 0x50,+R 16 % R16
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<a name="l233"></a> 0x50,+R 32 R32
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<a name="l234"></a> 0x50,+R 32 `R64
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<a name="l235"></a> 0xFF,/6 16 % RM16
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<a name="l236"></a> 0xFF,/6 32 RM32
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<a name="l237"></a> 0xFF,/6 32 RM64;
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<a name="l238"></a>OPCODE PUSHA 0x60, 16;
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<a name="l239"></a>OPCODE PUSHAD 0x60, 32;
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<a name="l240"></a>OPCODE PUSHF 0x9C, 16;
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<a name="l241"></a>OPCODE PUSHFD 0x9C, 32;
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<a name="l242"></a>OPCODE POP
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<a name="l243"></a> 0x1F, DS
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<a name="l244"></a> 0x07, ES
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<a name="l245"></a> 0x17, SS
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<a name="l246"></a> 0x0F 0xA1, FS
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<a name="l247"></a> 0x0F 0xA9, GS
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<a name="l248"></a> 0x58,+R 16 R16
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<a name="l249"></a> 0x58,+R 32 R32
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<a name="l250"></a> 0x58,+R 32 `R64
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<a name="l251"></a> 0x8F,/0 16 RM16
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<a name="l252"></a> 0x8F,/0 32 RM32
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<a name="l253"></a> 0x8F,/0 32 RM64;
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<a name="l254"></a>OPCODE POPA 0x61, 16;
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<a name="l255"></a>OPCODE POPAD 0x61, 32;
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<a name="l256"></a>OPCODE POPF 0x9D, 16;
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<a name="l257"></a>OPCODE POPFD 0x9D, 32;
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<a name="l258"></a>OPCODE MOV
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<a name="l259"></a>// 0xA0, AL MOFFS8
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<a name="l260"></a> 0xA1, 16 AX MOFFS16
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<a name="l261"></a> 0xA1, 32 EAX MOFFS32
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<a name="l262"></a>// 0xA2, MOFFS8 AL
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<a name="l263"></a> 0xA3, 16 MOFFS16 AX
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<a name="l264"></a> 0xA3, 32 MOFFS32 EAX
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<a name="l265"></a> 0x8A,/R R8 RM8
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<a name="l266"></a> 0x8B,/R 16 R16 RM16
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<a name="l267"></a> 0x8B,/R 32 R32 RM32
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<a name="l268"></a> 0x8B,/R 32 R64 RM64
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<a name="l269"></a> 0x88,/R RM8 R8
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<a name="l270"></a> 0x89,/R 16 RM16 R16
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<a name="l271"></a> 0x89,/R 32 RM32 R32
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<a name="l272"></a> 0x89,/R 32 RM64 R64
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<a name="l273"></a> 0x8C,/R 32 RM16 SREG
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<a name="l274"></a> 0x8E,/R 32 SREG RM16
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<a name="l275"></a> 0xB0,+R &R8 UIMM8
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<a name="l276"></a> 0xB0,+R R8 IMM8
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<a name="l277"></a> 0xB8,+R 16 &R16 UIMM16
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<a name="l278"></a> 0xB8,+R 16 R16 IMM16
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<a name="l279"></a> 0xB8,+R 32 &R32 UIMM32
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<a name="l280"></a> 0xB8,+R 32 R32 IMM32
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<a name="l281"></a> 0xB8,+R 32 `R64 UIMM32
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<a name="l282"></a> 0xB8,+R 32 &R64 UIMM64
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<a name="l283"></a> 0xB8,+R 32 R64 IMM64
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<a name="l284"></a> 0xC6, &RM8 UIMM8
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<a name="l285"></a> 0xC6, RM8 IMM8
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<a name="l286"></a> 0xC7, 16 &RM16 UIMM16
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<a name="l287"></a> 0xC7, 16 RM16 IMM16
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<a name="l288"></a> 0xC7, 32 &RM32 UIMM32
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<a name="l289"></a> 0xC7, 32 RM32 IMM32
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<a name="l290"></a> 0xC7, 32 `RM64 UIMM32
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<a name="l291"></a> 0xC7, 32 RM64 IMM32;
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<a name="l292"></a>
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<a name="l293"></a>OPCODE ADC
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<a name="l294"></a> 0x14, IB &AL UIMM8
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<a name="l295"></a> 0x14, IB AL IMM8
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<a name="l296"></a> 0x15, 16 IW &AX UIMM16
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<a name="l297"></a> 0x15, 16 IW AX IMM16
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<a name="l298"></a> 0x15, 32 ID &EAX UIMM32
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<a name="l299"></a> 0x15, 32 ID EAX IMM32
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<a name="l300"></a> 0x80,/2 IB RM8 IMM8
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<a name="l301"></a> 0x83,/2 16 IB RM16 IMM8
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<a name="l302"></a> 0x83,/2 32 IB RM32 IMM8
|
|
<a name="l303"></a> 0x83,/2 32 IB RM64 IMM8
|
|
<a name="l304"></a> 0x81,/2 16 IW RM16 IMM16
|
|
<a name="l305"></a> 0x81,/2 32 ID RM32 IMM32
|
|
<a name="l306"></a> 0x81,/2 32 ID RM64 IMM32
|
|
<a name="l307"></a> 0x12,/R R8 RM8
|
|
<a name="l308"></a> 0x13,/R 16 R16 RM16
|
|
<a name="l309"></a> 0x13,/R 32 R32 RM32
|
|
<a name="l310"></a> 0x13,/R 32 R64 RM64
|
|
<a name="l311"></a> 0x10,/R RM8 R8
|
|
<a name="l312"></a> 0x11,/R 16 RM16 R16
|
|
<a name="l313"></a> 0x11,/R 32 RM32 R32
|
|
<a name="l314"></a> 0x11,/R 32 RM64 R64;
|
|
<a name="l315"></a>OPCODE ADD
|
|
<a name="l316"></a> 0x04, IB &AL UIMM8
|
|
<a name="l317"></a> 0x04, IB AL IMM8
|
|
<a name="l318"></a> 0x05, 16 IW &AX UIMM16
|
|
<a name="l319"></a> 0x05, 16 IW AX IMM16
|
|
<a name="l320"></a> 0x05, 32 ID &EAX UIMM32
|
|
<a name="l321"></a> 0x05, 32 ID EAX IMM32
|
|
<a name="l322"></a> 0x80,/0 IB &RM8 UIMM8
|
|
<a name="l323"></a> 0x80,/0 IB RM8 IMM8
|
|
<a name="l324"></a> 0x83,/0 16 IB RM16 IMM8
|
|
<a name="l325"></a> 0x83,/0 32 IB RM32 IMM8
|
|
<a name="l326"></a> 0x83,/0 32 IB RM64 IMM8
|
|
<a name="l327"></a> 0x81,/0 16 IW RM16 IMM16
|
|
<a name="l328"></a> 0x81,/0 32 ID RM32 IMM32
|
|
<a name="l329"></a> 0x81,/0 32 ID RM64 IMM32
|
|
<a name="l330"></a> 0x02,/R R8 RM8
|
|
<a name="l331"></a> 0x03,/R 16 R16 RM16
|
|
<a name="l332"></a> 0x03,/R 32 R32 RM32
|
|
<a name="l333"></a> 0x03,/R 32 R64 RM64
|
|
<a name="l334"></a> 0x00,/R RM8 R8
|
|
<a name="l335"></a> 0x01,/R 16 RM16 R16
|
|
<a name="l336"></a> 0x01,/R 32 RM32 R32
|
|
<a name="l337"></a> 0x01,/R 32 RM64 R64;
|
|
<a name="l338"></a>OPCODE AND
|
|
<a name="l339"></a> 0x24, IB &AL UIMM8
|
|
<a name="l340"></a> 0x24, IB AL IMM8
|
|
<a name="l341"></a> 0x25, 16 IW &AX UIMM16
|
|
<a name="l342"></a> 0x25, 16 IW AX IMM16
|
|
<a name="l343"></a> 0x25, 32 ID &EAX UIMM32
|
|
<a name="l344"></a> 0x25, 32 ID EAX IMM32
|
|
<a name="l345"></a> 0x80,/4 IB &RM8 UIMM8
|
|
<a name="l346"></a> 0x80,/4 IB RM8 IMM8
|
|
<a name="l347"></a> 0x83,/4 16 IB RM16 IMM8
|
|
<a name="l348"></a> 0x83,/4 32 IB RM32 IMM8
|
|
<a name="l349"></a> 0x83,/4 32 IB RM64 IMM8
|
|
<a name="l350"></a> 0x81,/4 16 IW RM16 IMM16
|
|
<a name="l351"></a> 0x81,/4 32 ID RM32 IMM32
|
|
<a name="l352"></a> 0x81,/4 32 ID RM64 IMM32
|
|
<a name="l353"></a> 0x22,/R R8 RM8
|
|
<a name="l354"></a> 0x23,/R 16 R16 RM16
|
|
<a name="l355"></a> 0x23,/R 32 R32 RM32
|
|
<a name="l356"></a> 0x23,/R 32 R64 RM64
|
|
<a name="l357"></a> 0x20,/R RM8 R8
|
|
<a name="l358"></a> 0x21,/R 16 RM16 R16
|
|
<a name="l359"></a> 0x21,/R 32 RM32 R32
|
|
<a name="l360"></a> 0x21,/R 32 RM64 R64;
|
|
<a name="l361"></a>OPCODE CMP
|
|
<a name="l362"></a> 0x3C, IB &AL UIMM8
|
|
<a name="l363"></a> 0x3C, IB AL IMM8
|
|
<a name="l364"></a> 0x3D, 16 IW &AX UIMM16
|
|
<a name="l365"></a> 0x3D, 16 IW AX IMM16
|
|
<a name="l366"></a> 0x3D, 32 ID &EAX UIMM32
|
|
<a name="l367"></a> 0x3D, 32 ID EAX IMM32
|
|
<a name="l368"></a> 0x80,/7 IB &RM8 UIMM8
|
|
<a name="l369"></a> 0x80,/7 IB RM8 IMM8
|
|
<a name="l370"></a> 0x83,/7 16 IB RM16 IMM8
|
|
<a name="l371"></a> 0x83,/7 32 IB RM32 IMM8
|
|
<a name="l372"></a> 0x83,/7 32 IB RM64 IMM8
|
|
<a name="l373"></a> 0x81,/7 16 IW RM16 IMM16
|
|
<a name="l374"></a> 0x81,/7 32 ID RM32 IMM32
|
|
<a name="l375"></a> 0x81,/7 32 ID RM64 IMM32
|
|
<a name="l376"></a> 0x3A,/R R8 RM8
|
|
<a name="l377"></a> 0x3B,/R 16 R16 RM16 //ERROR?
|
|
<a name="l378"></a> 0x3B,/R 32 R32 RM32
|
|
<a name="l379"></a> 0x3B,/R 32 R64 RM64
|
|
<a name="l380"></a> 0x38,/R RM8 R8
|
|
<a name="l381"></a> 0x39,/R 16 RM16 R16
|
|
<a name="l382"></a> 0x39,/R 32 RM32 R32
|
|
<a name="l383"></a> 0x39,/R 32 RM64 R64;
|
|
<a name="l384"></a>OPCODE OR
|
|
<a name="l385"></a> 0x0C, IB &AL UIMM8
|
|
<a name="l386"></a> 0x0C, IB AL IMM8
|
|
<a name="l387"></a> 0x0D, 16 IW &AX UIMM16
|
|
<a name="l388"></a> 0x0D, 16 IW AX IMM16
|
|
<a name="l389"></a> 0x0D, 32 ID &EAX UIMM32
|
|
<a name="l390"></a> 0x0D, 32 ID EAX IMM32
|
|
<a name="l391"></a> 0x80,/1 IB &RM8 UIMM8
|
|
<a name="l392"></a> 0x80,/1 IB RM8 IMM8
|
|
<a name="l393"></a> 0x83,/1 16 IB RM16 IMM8
|
|
<a name="l394"></a> 0x83,/1 32 IB RM32 IMM8
|
|
<a name="l395"></a> 0x83,/1 32 IB RM64 IMM8
|
|
<a name="l396"></a> 0x81,/1 16 IW RM16 IMM16
|
|
<a name="l397"></a> 0x81,/1 32 ID RM32 IMM32
|
|
<a name="l398"></a> 0x81,/1 32 ID RM64 IMM32
|
|
<a name="l399"></a> 0x0A,/R R8 RM8
|
|
<a name="l400"></a> 0x0B,/R 16 R16 RM16
|
|
<a name="l401"></a> 0x0B,/R 32 R32 RM32
|
|
<a name="l402"></a> 0x0B,/R 32 R64 RM64
|
|
<a name="l403"></a> 0x08,/R RM8 R8
|
|
<a name="l404"></a> 0x09,/R 16 RM16 R16
|
|
<a name="l405"></a> 0x09,/R 32 RM32 R32
|
|
<a name="l406"></a> 0x09,/R 32 RM64 R64;
|
|
<a name="l407"></a>OPCODE SBB
|
|
<a name="l408"></a> 0x1C, IB &AL UIMM8
|
|
<a name="l409"></a> 0x1C, IB AL IMM8
|
|
<a name="l410"></a> 0x1D, 16 IW &AX UIMM16
|
|
<a name="l411"></a> 0x1D, 16 IW AX IMM16
|
|
<a name="l412"></a> 0x1D, 32 ID &EAX UIMM32
|
|
<a name="l413"></a> 0x1D, 32 ID EAX IMM32
|
|
<a name="l414"></a> 0x80,/3 IB &RM8 UIMM8
|
|
<a name="l415"></a> 0x80,/3 IB RM8 IMM8
|
|
<a name="l416"></a> 0x83,/3 16 IB RM16 IMM8
|
|
<a name="l417"></a> 0x83,/3 32 IB RM32 IMM8
|
|
<a name="l418"></a> 0x83,/3 32 IB RM64 IMM8
|
|
<a name="l419"></a> 0x81,/3 16 IW RM16 IMM16
|
|
<a name="l420"></a> 0x81,/3 32 ID RM32 IMM32
|
|
<a name="l421"></a> 0x81,/3 32 ID RM64 IMM32
|
|
<a name="l422"></a> 0x1A,/R R8 RM8
|
|
<a name="l423"></a> 0x1B,/R 16 R16 RM16
|
|
<a name="l424"></a> 0x1B,/R 32 R32 RM32
|
|
<a name="l425"></a> 0x1B,/R 32 R64 RM64
|
|
<a name="l426"></a> 0x18,/R RM8 R8
|
|
<a name="l427"></a> 0x19,/R 16 RM16 R16
|
|
<a name="l428"></a> 0x19,/R 32 RM32 R32
|
|
<a name="l429"></a> 0x19,/R 32 RM64 R64;
|
|
<a name="l430"></a>OPCODE SUB
|
|
<a name="l431"></a> 0x2C, IB &AL UIMM8
|
|
<a name="l432"></a> 0x2C, IB AL IMM8
|
|
<a name="l433"></a> 0x2D, 16 IW &AX UIMM16
|
|
<a name="l434"></a> 0x2D, 16 IW AX IMM16
|
|
<a name="l435"></a> 0x2D, 32 ID &EAX UIMM32
|
|
<a name="l436"></a> 0x2D, 32 ID EAX IMM32
|
|
<a name="l437"></a> 0x80,/5 IB &RM8 UIMM8
|
|
<a name="l438"></a> 0x80,/5 IB RM8 IMM8
|
|
<a name="l439"></a> 0x83,/5 16 IB RM16 IMM8
|
|
<a name="l440"></a> 0x83,/5 32 IB RM32 IMM8
|
|
<a name="l441"></a> 0x83,/5 32 IB RM64 IMM8
|
|
<a name="l442"></a> 0x81,/5 16 IW RM16 IMM16
|
|
<a name="l443"></a> 0x81,/5 32 ID RM32 IMM32
|
|
<a name="l444"></a> 0x81,/5 32 ID RM64 IMM32
|
|
<a name="l445"></a> 0x2A,/R R8 RM8
|
|
<a name="l446"></a> 0x2B,/R 16 R16 RM16
|
|
<a name="l447"></a> 0x2B,/R 32 R32 RM32
|
|
<a name="l448"></a> 0x2B,/R 32 R64 RM64
|
|
<a name="l449"></a> 0x28,/R RM8 R8
|
|
<a name="l450"></a> 0x29,/R 16 RM16 R16
|
|
<a name="l451"></a> 0x29,/R 32 RM32 R32
|
|
<a name="l452"></a> 0x29,/R 32 RM64 R64;
|
|
<a name="l453"></a>OPCODE TEST
|
|
<a name="l454"></a> 0xA8, IB &AL UIMM8
|
|
<a name="l455"></a> 0xA8, IB AL IMM8
|
|
<a name="l456"></a> 0xA9, 16 IW &AX UIMM16
|
|
<a name="l457"></a> 0xA9, 16 IW AX IMM16
|
|
<a name="l458"></a> 0xA9, 32 ID &EAX UIMM32
|
|
<a name="l459"></a> 0xA9, 32 ID EAX IMM32
|
|
<a name="l460"></a> 0xF6,/0 IB &RM8 UIMM8
|
|
<a name="l461"></a> 0xF6,/0 IB RM8 IMM8
|
|
<a name="l462"></a> 0xF7,/0 16 IW RM16 IMM16
|
|
<a name="l463"></a> 0xF7,/0 32 ID RM32 IMM32
|
|
<a name="l464"></a> 0xF7,/0 32 ID RM64 IMM32
|
|
<a name="l465"></a> 0x84,/R RM8 R8
|
|
<a name="l466"></a> 0x85,/R 16 RM16 R16
|
|
<a name="l467"></a> 0x85,/R 32 RM32 R32
|
|
<a name="l468"></a> 0x85,/R 32 RM64 R64;
|
|
<a name="l469"></a>OPCODE NOP 0x90;
|
|
<a name="l470"></a>OPCODE NOP2 0x66 0x90;
|
|
<a name="l471"></a>OPCODE XCHG
|
|
<a name="l472"></a> 0x90,+R 16 R16 AX
|
|
<a name="l473"></a> 0x90,+R 16 AX R16
|
|
<a name="l474"></a> 0x90,+R 32 R32 EAX
|
|
<a name="l475"></a> 0x90,+R 32 EAX R32
|
|
<a name="l476"></a> 0x90,+R 32 R64 RAX
|
|
<a name="l477"></a> 0x90,+R 32 RAX R64
|
|
<a name="l478"></a> 0x86,/R R8 RM8
|
|
<a name="l479"></a> 0x87,/R 16 R16 RM16
|
|
<a name="l480"></a> 0x87,/R 32 R32 RM32
|
|
<a name="l481"></a> 0x87,/R 32 R64 RM64
|
|
<a name="l482"></a> 0x86,/R RM8 R8
|
|
<a name="l483"></a> 0x87,/R 16 RM16 R16
|
|
<a name="l484"></a> 0x87,/R 32 RM32 R32
|
|
<a name="l485"></a> 0x87,/R 32 RM64 R64;
|
|
<a name="l486"></a>OPCODE XOR
|
|
<a name="l487"></a> 0x34, IB &AL UIMM8
|
|
<a name="l488"></a> 0x34, IB AL IMM8
|
|
<a name="l489"></a> 0x35, 16 IW &AX UIMM16
|
|
<a name="l490"></a> 0x35, 16 IW AX IMM16
|
|
<a name="l491"></a> 0x35, 32 ID &EAX UIMM32
|
|
<a name="l492"></a> 0x35, 32 ID EAX IMM32
|
|
<a name="l493"></a> 0x80,/6 IB &RM8 UIMM8
|
|
<a name="l494"></a> 0x80,/6 IB RM8 IMM8
|
|
<a name="l495"></a> 0x83,/6 16 IB RM16 IMM8
|
|
<a name="l496"></a> 0x83,/6 32 IB RM32 IMM8
|
|
<a name="l497"></a> 0x83,/6 32 IB RM64 IMM8
|
|
<a name="l498"></a> 0x81,/6 16 IW RM16 IMM16
|
|
<a name="l499"></a> 0x81,/6 32 ID RM32 IMM32
|
|
<a name="l500"></a> 0x81,/6 32 ID RM64 IMM32
|
|
<a name="l501"></a> 0x32,/R R8 RM8
|
|
<a name="l502"></a> 0x33,/R 16 R16 RM16
|
|
<a name="l503"></a> 0x33,/R 32 R32 RM32
|
|
<a name="l504"></a> 0x33,/R 32 ^ R64 RM64
|
|
<a name="l505"></a> 0x30,/R RM8 R8
|
|
<a name="l506"></a> 0x31,/R 16 RM16 R16
|
|
<a name="l507"></a> 0x31,/R 32 RM32 R32
|
|
<a name="l508"></a> 0x31,/R 32 ^ RM64 R64;
|
|
<a name="l509"></a>
|
|
<a name="l510"></a>OPCODE CMOVO
|
|
<a name="l511"></a> 0x0F 0x40,/R 16 R16 RM16
|
|
<a name="l512"></a> 0x0F 0x40,/R 32 R32 RM32
|
|
<a name="l513"></a> 0x0F 0x40,/R 32 R64 RM64;
|
|
<a name="l514"></a>OPCODE CMOVNO
|
|
<a name="l515"></a> 0x0F 0x41,/R 16 R16 RM16
|
|
<a name="l516"></a> 0x0F 0x41,/R 32 R32 RM32
|
|
<a name="l517"></a> 0x0F 0x41,/R 32 R64 RM64;
|
|
<a name="l518"></a>OPCODE CMOVB
|
|
<a name="l519"></a> 0x0F 0x42,/R 16 R16 RM16
|
|
<a name="l520"></a> 0x0F 0x42,/R 32 R32 RM32
|
|
<a name="l521"></a> 0x0F 0x42,/R 32 R64 RM64 :CMOVC CMOVNAE;
|
|
<a name="l522"></a>OPCODE CMOVAE
|
|
<a name="l523"></a> 0x0F 0x43,/R 16 R16 RM16
|
|
<a name="l524"></a> 0x0F 0x43,/R 32 R32 RM32
|
|
<a name="l525"></a> 0x0F 0x43,/R 32 R64 RM64 :CMOVNB CMOVNC;
|
|
<a name="l526"></a>OPCODE CMOVE
|
|
<a name="l527"></a> 0x0F 0x44,/R 16 R16 RM16
|
|
<a name="l528"></a> 0x0F 0x44,/R 32 R32 RM32
|
|
<a name="l529"></a> 0x0F 0x44,/R 32 R64 RM64 :CMOVZ;
|
|
<a name="l530"></a>OPCODE CMOVNE
|
|
<a name="l531"></a> 0x0F 0x45,/R 16 R16 RM16
|
|
<a name="l532"></a> 0x0F 0x45,/R 32 R32 RM32
|
|
<a name="l533"></a> 0x0F 0x45,/R 32 R64 RM64 :CMOVNZ;
|
|
<a name="l534"></a>OPCODE CMOVBE
|
|
<a name="l535"></a> 0x0F 0x46,/R 16 R16 RM16
|
|
<a name="l536"></a> 0x0F 0x46,/R 32 R32 RM32
|
|
<a name="l537"></a> 0x0F 0x46,/R 32 R64 RM64 :CMOVNA;
|
|
<a name="l538"></a>OPCODE CMOVA
|
|
<a name="l539"></a> 0x0F 0x47,/R 16 R16 RM16
|
|
<a name="l540"></a> 0x0F 0x47,/R 32 R32 RM32
|
|
<a name="l541"></a> 0x0F 0x47,/R 32 R64 RM64 :CMOVNBE;
|
|
<a name="l542"></a>OPCODE CMOVS
|
|
<a name="l543"></a> 0x0F 0x48,/R 16 R16 RM16
|
|
<a name="l544"></a> 0x0F 0x48,/R 32 R32 RM32
|
|
<a name="l545"></a> 0x0F 0x48,/R 32 R64 RM64;
|
|
<a name="l546"></a>OPCODE CMOVNS
|
|
<a name="l547"></a> 0x0F 0x49,/R 16 R16 RM16
|
|
<a name="l548"></a> 0x0F 0x49,/R 32 R32 RM32
|
|
<a name="l549"></a> 0x0F 0x49,/R 32 R64 RM64;
|
|
<a name="l550"></a>OPCODE CMOVP
|
|
<a name="l551"></a> 0x0F 0x4A,/R 16 R16 RM16
|
|
<a name="l552"></a> 0x0F 0x4A,/R 32 R32 RM32
|
|
<a name="l553"></a> 0x0F 0x4A,/R 32 R64 RM64 :CMOVPE;
|
|
<a name="l554"></a>OPCODE CMOVNP
|
|
<a name="l555"></a> 0x0F 0x4B,/R 16 R16 RM16
|
|
<a name="l556"></a> 0x0F 0x4B,/R 32 R32 RM32
|
|
<a name="l557"></a> 0x0F 0x4B,/R 32 R64 RM64 :CMOVPO;
|
|
<a name="l558"></a>OPCODE CMOVL
|
|
<a name="l559"></a> 0x0F 0x4C,/R 16 R16 RM16
|
|
<a name="l560"></a> 0x0F 0x4C,/R 32 R32 RM32
|
|
<a name="l561"></a> 0x0F 0x4C,/R 32 R64 RM64 :CMOVNGE;
|
|
<a name="l562"></a>OPCODE CMOVGE
|
|
<a name="l563"></a> 0x0F 0x4D,/R 16 R16 RM16
|
|
<a name="l564"></a> 0x0F 0x4D,/R 32 R32 RM32
|
|
<a name="l565"></a> 0x0F 0x4D,/R 32 R64 RM64 :CMOVNL;
|
|
<a name="l566"></a>OPCODE CMOVLE
|
|
<a name="l567"></a> 0x0F 0x4E,/R 16 R16 RM16
|
|
<a name="l568"></a> 0x0F 0x4E,/R 32 R32 RM32
|
|
<a name="l569"></a> 0x0F 0x4E,/R 32 R64 RM64 :CMOVNG;
|
|
<a name="l570"></a>OPCODE CMOVG
|
|
<a name="l571"></a> 0x0F 0x4F,/R 16 R16 RM16
|
|
<a name="l572"></a> 0x0F 0x4F,/R 32 R32 RM32
|
|
<a name="l573"></a> 0x0F 0x4F,/R 32 R64 RM64 :CMOVNLE;
|
|
<a name="l574"></a>
|
|
<a name="l575"></a>OPCODE CALL
|
|
<a name="l576"></a> 0xE8, 16 !&CW REL16
|
|
<a name="l577"></a> 0xFF,/2 16 ! RM16
|
|
<a name="l578"></a> 0xE8, 32 !&CD REL32
|
|
<a name="l579"></a> 0xFF,/2 32 ! RM32
|
|
<a name="l580"></a> 0xFF,/2 32 !`RM64
|
|
<a name="l581"></a>// 0x9A, CD PTR1616
|
|
<a name="l582"></a>// 0xFF,/3 16 M1616
|
|
<a name="l583"></a>// 0x9A, 16 CP PTR1632
|
|
<a name="l584"></a>// 0x9A, 32 CP PTR3232
|
|
<a name="l585"></a>// 0xFF,/3 32 M1632
|
|
<a name="l586"></a>;
|
|
<a name="l587"></a>
|
|
<a name="l588"></a>OPCODE JMP
|
|
<a name="l589"></a> 0xEB, &CB REL8
|
|
<a name="l590"></a> 0xE9, 16 !CW REL16
|
|
<a name="l591"></a> 0xE9, 32 !CD REL32
|
|
<a name="l592"></a> 0xFF,/4 16 ! RM16
|
|
<a name="l593"></a> 0xFF,/4 32 ! RM32
|
|
<a name="l594"></a> 0xFF,/4 32 ! RM64;
|
|
<a name="l595"></a>
|
|
<a name="l596"></a>OPCODE JO
|
|
<a name="l597"></a> 0x70, &CB REL8
|
|
<a name="l598"></a> 0x0F 0x80, 16 !CW REL16
|
|
<a name="l599"></a> 0x0F 0x80, 32 !CD REL32;
|
|
<a name="l600"></a>OPCODE JNO
|
|
<a name="l601"></a> 0x71, &CB REL8
|
|
<a name="l602"></a> 0x0F 0x81, 16 !CW REL16
|
|
<a name="l603"></a> 0x0F 0x81, 32 !CD REL32;
|
|
<a name="l604"></a>OPCODE JB
|
|
<a name="l605"></a> 0x72, &CB REL8
|
|
<a name="l606"></a> 0x0F 0x82, 16 !CW REL16
|
|
<a name="l607"></a> 0x0F 0x82, 32 !CD REL32 :JC JNAE;
|
|
<a name="l608"></a>OPCODE JAE
|
|
<a name="l609"></a> 0x73, &CB REL8
|
|
<a name="l610"></a> 0x0F 0x83, 16 !CW REL16
|
|
<a name="l611"></a> 0x0F 0x83, 32 !CD REL32 :JNB JNC;
|
|
<a name="l612"></a>OPCODE JE
|
|
<a name="l613"></a> 0x74, &CB REL8
|
|
<a name="l614"></a> 0x0F 0x84, 16 !CW REL16
|
|
<a name="l615"></a> 0x0F 0x84, 32 !CD REL32 :JZ;
|
|
<a name="l616"></a>OPCODE JNE
|
|
<a name="l617"></a> 0x75, &CB REL8
|
|
<a name="l618"></a> 0x0F 0x85, 16 !CW REL16
|
|
<a name="l619"></a> 0x0F 0x85, 32 !CD REL32 :JNZ;
|
|
<a name="l620"></a>OPCODE JBE
|
|
<a name="l621"></a> 0x76, &CB REL8
|
|
<a name="l622"></a> 0x0F 0x86, 16 !CW REL16
|
|
<a name="l623"></a> 0x0F 0x86, 32 !CD REL32 :JNA;
|
|
<a name="l624"></a>OPCODE JA
|
|
<a name="l625"></a> 0x77, &CB REL8
|
|
<a name="l626"></a> 0x0F 0x87, 16 !CW REL16
|
|
<a name="l627"></a> 0x0F 0x87, 32 !CD REL32 :JNBE;
|
|
<a name="l628"></a>OPCODE JS
|
|
<a name="l629"></a> 0x78, &CB REL8
|
|
<a name="l630"></a> 0x0F 0x88, 16 !CW REL16
|
|
<a name="l631"></a> 0x0F 0x88, 32 !CD REL32;
|
|
<a name="l632"></a>OPCODE JNS
|
|
<a name="l633"></a> 0x79, &CB REL8
|
|
<a name="l634"></a> 0x0F 0x89, 16 !CW REL16
|
|
<a name="l635"></a> 0x0F 0x89, 32 !CD REL32;
|
|
<a name="l636"></a>OPCODE JP
|
|
<a name="l637"></a> 0x7A, &CB REL8
|
|
<a name="l638"></a> 0x0F 0x8A, 16 !CW REL16
|
|
<a name="l639"></a> 0x0F 0x8A, 32 !CD REL32 :JPE;
|
|
<a name="l640"></a>OPCODE JNP
|
|
<a name="l641"></a> 0x7B, &CB REL8
|
|
<a name="l642"></a> 0x0F 0x8B, 16 !CW REL16
|
|
<a name="l643"></a> 0x0F 0x8B, 32 !CD REL32 :JPO;
|
|
<a name="l644"></a>OPCODE JL
|
|
<a name="l645"></a> 0x7C, &CB REL8
|
|
<a name="l646"></a> 0x0F 0x8C, 16 !CW REL16
|
|
<a name="l647"></a> 0x0F 0x8C, 32 !CD REL32 :JNGE;
|
|
<a name="l648"></a>OPCODE JGE
|
|
<a name="l649"></a> 0x7D, &CB REL8
|
|
<a name="l650"></a> 0x0F 0x8D, 16 !CW REL16
|
|
<a name="l651"></a> 0x0F 0x8D, 32 !CD REL32 :JNL;
|
|
<a name="l652"></a>OPCODE JLE
|
|
<a name="l653"></a> 0x7E, &CB REL8
|
|
<a name="l654"></a> 0x0F 0x8E, 16 !CW REL16
|
|
<a name="l655"></a> 0x0F 0x8E, 32 !CD REL32 :JNG;
|
|
<a name="l656"></a>OPCODE JG
|
|
<a name="l657"></a> 0x7F, &CB REL8
|
|
<a name="l658"></a> 0x0F 0x8F, 16 !CW REL16
|
|
<a name="l659"></a> 0x0F 0x8F, 32 !CD REL32 :JNLE;
|
|
<a name="l660"></a>
|
|
<a name="l661"></a>OPCODE JCXZ
|
|
<a name="l662"></a> 0xE3, CB REL8 :JECXZ JRCXZ;
|
|
<a name="l663"></a>
|
|
<a name="l664"></a>OPCODE INC
|
|
<a name="l665"></a> 0x40,+R 16 % R16
|
|
<a name="l666"></a> 0x40,+R 32 % R32
|
|
<a name="l667"></a> 0xFE,/0 RM8
|
|
<a name="l668"></a> 0xFF,/0 16 RM16
|
|
<a name="l669"></a> 0xFF,/0 32 RM32
|
|
<a name="l670"></a> 0xFF,/0 32 RM64;
|
|
<a name="l671"></a>OPCODE DEC
|
|
<a name="l672"></a> 0x48,+R 16 % R16
|
|
<a name="l673"></a> 0x48,+R 32 % R32
|
|
<a name="l674"></a> 0xFE,/1 RM8
|
|
<a name="l675"></a> 0xFF,/1 16 RM16
|
|
<a name="l676"></a> 0xFF,/1 32 RM32
|
|
<a name="l677"></a> 0xFF,/1 32 RM64;
|
|
<a name="l678"></a>OPCODE NOT
|
|
<a name="l679"></a> 0xF6,/2 RM8
|
|
<a name="l680"></a> 0xF7,/2 16 RM16
|
|
<a name="l681"></a> 0xF7,/2 32 RM32
|
|
<a name="l682"></a> 0xF7,/2 32 RM64;
|
|
<a name="l683"></a>OPCODE NEG
|
|
<a name="l684"></a> 0xF6,/3 RM8
|
|
<a name="l685"></a> 0xF7,/3 16 RM16
|
|
<a name="l686"></a> 0xF7,/3 32 RM32
|
|
<a name="l687"></a> 0xF7,/3 32 RM64;
|
|
<a name="l688"></a>OPCODE MUL
|
|
<a name="l689"></a> 0xF6,/4 RM8
|
|
<a name="l690"></a> 0xF7,/4 16 RM16
|
|
<a name="l691"></a> 0xF7,/4 32 RM32
|
|
<a name="l692"></a> 0xF7,/4 32 RM64;
|
|
<a name="l693"></a>OPCODE IMUL
|
|
<a name="l694"></a> 0xF6,/5 RM8
|
|
<a name="l695"></a> 0xF7,/5 16 RM16
|
|
<a name="l696"></a> 0xF7,/5 32 RM32
|
|
<a name="l697"></a> 0xF7,/5 32 RM64;
|
|
<a name="l698"></a>OPCODE IMUL2
|
|
<a name="l699"></a> 0x0F 0xAF,/R 16 R16 RM16
|
|
<a name="l700"></a> 0x0F 0xAF,/R 32 R32 RM32
|
|
<a name="l701"></a> 0x0F 0xAF,/R 32 R64 RM64
|
|
<a name="l702"></a> 0x6B,/R 16 IB RM16 IMM8
|
|
<a name="l703"></a> 0x6B,/R 32 IB RM32 IMM8
|
|
<a name="l704"></a> 0x6B,/R 32 IB RM64 IMM8
|
|
<a name="l705"></a> 0x69,/R 16 IW &RM16 UIMM16
|
|
<a name="l706"></a> 0x69,/R 16 IW RM16 IMM16
|
|
<a name="l707"></a> 0x69,/R 32 ID &RM32 UIMM32
|
|
<a name="l708"></a> 0x69,/R 32 ID RM32 IMM32
|
|
<a name="l709"></a> 0x69,/R 32 ID &RM64 UIMM32
|
|
<a name="l710"></a> 0x69,/R 32 ID RM64 IMM32;
|
|
<a name="l711"></a>OPCODE DIV
|
|
<a name="l712"></a> 0xF6,/6 RM8
|
|
<a name="l713"></a> 0xF7,/6 16 RM16
|
|
<a name="l714"></a> 0xF7,/6 32 RM32
|
|
<a name="l715"></a> 0xF7,/6 32 RM64;
|
|
<a name="l716"></a>OPCODE IDIV
|
|
<a name="l717"></a> 0xF6,/7 RM8
|
|
<a name="l718"></a> 0xF7,/7 16 RM16
|
|
<a name="l719"></a> 0xF7,/7 32 RM32
|
|
<a name="l720"></a> 0xF7,/7 32 RM64;
|
|
<a name="l721"></a>
|
|
<a name="l722"></a>OPCODE AAA 0x37;
|
|
<a name="l723"></a>OPCODE AAD 0xD5 0x0A;
|
|
<a name="l724"></a>OPCODE AAM 0xD4 0x0A;
|
|
<a name="l725"></a>OPCODE AAS 0x3F;
|
|
<a name="l726"></a>OPCODE ARPL 0x63,/R RM16 R16;
|
|
<a name="l727"></a>OPCODE BOUND
|
|
<a name="l728"></a> 0x62,/R 16 RM16 R16
|
|
<a name="l729"></a> 0x62,/R 32 RM32 R32
|
|
<a name="l730"></a> 0x62,/R 32 RM64 R64;
|
|
<a name="l731"></a>OPCODE BSF
|
|
<a name="l732"></a> 0x0F 0xBC,/R 16 R16 RM16
|
|
<a name="l733"></a> 0x0F 0xBC,/R 32 R32 RM32
|
|
<a name="l734"></a> 0x0F 0xBC,/R 32 R64 RM64;
|
|
<a name="l735"></a>OPCODE BSR
|
|
<a name="l736"></a> 0x0F 0xBD,/R 16 R16 RM16
|
|
<a name="l737"></a> 0x0F 0xBD,/R 32 R32 RM32
|
|
<a name="l738"></a> 0x0F 0xBD,/R 32 R64 RM64;
|
|
<a name="l739"></a>OPCODE BSWAP
|
|
<a name="l740"></a> 0x0F 0xC8,/R 32 R32
|
|
<a name="l741"></a> 0x0F 0xC8,/R 32 R64;
|
|
<a name="l742"></a>OPCODE BT
|
|
<a name="l743"></a> 0x0F 0xA3,/R 16 RM16 R16
|
|
<a name="l744"></a> 0x0F 0xA3,/R 32 RM32 R32
|
|
<a name="l745"></a> 0x0F 0xA3,/R 32 RM64 R64
|
|
<a name="l746"></a> 0x0F 0xBA,/4 16 IB &RM16 UIMM8
|
|
<a name="l747"></a> 0x0F 0xBA,/4 16 IB RM16 IMM8
|
|
<a name="l748"></a> 0x0F 0xBA,/4 32 IB &RM32 UIMM8
|
|
<a name="l749"></a> 0x0F 0xBA,/4 32 IB RM32 IMM8
|
|
<a name="l750"></a> 0x0F 0xBA,/4 32 IB &RM64 UIMM8
|
|
<a name="l751"></a> 0x0F 0xBA,/4 32 IB RM64 IMM8;
|
|
<a name="l752"></a>OPCODE BTC
|
|
<a name="l753"></a> 0x0F 0xBB,/R 16 RM16 R16
|
|
<a name="l754"></a> 0x0F 0xBB,/R 32 RM32 R32
|
|
<a name="l755"></a> 0x0F 0xBB,/R 32 RM64 R64
|
|
<a name="l756"></a> 0x0F 0xBA,/7 16 IB &RM16 UIMM8
|
|
<a name="l757"></a> 0x0F 0xBA,/7 16 IB RM16 IMM8
|
|
<a name="l758"></a> 0x0F 0xBA,/7 32 IB &RM32 UIMM8
|
|
<a name="l759"></a> 0x0F 0xBA,/7 32 IB RM32 IMM8
|
|
<a name="l760"></a> 0x0F 0xBA,/7 32 IB &RM64 UIMM8
|
|
<a name="l761"></a> 0x0F 0xBA,/7 32 IB RM64 IMM8;
|
|
<a name="l762"></a>OPCODE BTR
|
|
<a name="l763"></a> 0x0F 0xB3,/R 16 RM16 R16
|
|
<a name="l764"></a> 0x0F 0xB3,/R 32 RM32 R32
|
|
<a name="l765"></a> 0x0F 0xB3,/R 32 RM64 R64
|
|
<a name="l766"></a> 0x0F 0xBA,/6 16 IB &RM16 UIMM8
|
|
<a name="l767"></a> 0x0F 0xBA,/6 16 IB RM16 IMM8
|
|
<a name="l768"></a> 0x0F 0xBA,/6 32 IB &RM32 UIMM8
|
|
<a name="l769"></a> 0x0F 0xBA,/6 32 IB RM32 IMM8
|
|
<a name="l770"></a> 0x0F 0xBA,/6 32 IB &RM64 UIMM8
|
|
<a name="l771"></a> 0x0F 0xBA,/6 32 IB RM64 IMM8;
|
|
<a name="l772"></a>OPCODE BTS
|
|
<a name="l773"></a> 0x0F 0xAB,/R 16 RM16 R16
|
|
<a name="l774"></a> 0x0F 0xAB,/R 32 RM32 R32
|
|
<a name="l775"></a> 0x0F 0xAB,/R 32 RM64 R64
|
|
<a name="l776"></a> 0x0F 0xBA,/5 16 IB &RM16 UIMM8
|
|
<a name="l777"></a> 0x0F 0xBA,/5 16 IB RM16 IMM8
|
|
<a name="l778"></a> 0x0F 0xBA,/5 32 IB &RM32 UIMM8
|
|
<a name="l779"></a> 0x0F 0xBA,/5 32 IB RM32 IMM8
|
|
<a name="l780"></a> 0x0F 0xBA,/5 32 IB &RM64 UIMM8
|
|
<a name="l781"></a> 0x0F 0xBA,/5 32 IB RM64 IMM8;
|
|
<a name="l782"></a>OPCODE POPCNT
|
|
<a name="l783"></a> 0xF3 0x0F 0xB8,/R 16 R16 RM16
|
|
<a name="l784"></a> 0xF3 0x0F 0xB8,/R 32 R32 RM32
|
|
<a name="l785"></a> 0xF3 0x48 0x0F 0xB8,/R 32 R64 RM64;
|
|
<a name="l786"></a>
|
|
<a name="l787"></a>OPCODE CBW 0x98, 16;
|
|
<a name="l788"></a>OPCODE CWDE 0x98, 32;
|
|
<a name="l789"></a>OPCODE CDQE 0x98, 32=;
|
|
<a name="l790"></a>OPCODE CWD 0x99, 16;
|
|
<a name="l791"></a>OPCODE CDQ 0x99, 32;
|
|
<a name="l792"></a>OPCODE CQO 0x99, 32=;
|
|
<a name="l793"></a>OPCODE CLC 0xF8;
|
|
<a name="l794"></a>OPCODE CLD 0xFC;
|
|
<a name="l795"></a>OPCODE CLI 0xFA;
|
|
<a name="l796"></a>OPCODE CLTS 0x0F 0x06;
|
|
<a name="l797"></a>OPCODE CMC 0xF5;
|
|
<a name="l798"></a>OPCODE CMPSB 0xA6;
|
|
<a name="l799"></a>OPCODE CMPSW 0xA7, 16;
|
|
<a name="l800"></a>OPCODE CMPSD 0xA7, 32;
|
|
<a name="l801"></a>OPCODE CMPSQ 0xA7, 32=;
|
|
<a name="l802"></a>OPCODE CMPXCHG
|
|
<a name="l803"></a> 0x0F 0xB0,/R RM8 R8
|
|
<a name="l804"></a> 0x0F 0xB1,/R 16 RM16 R16
|
|
<a name="l805"></a> 0x0F 0xB1,/R 32 RM32 R32
|
|
<a name="l806"></a> 0x0F 0xB1,/R 32 RM64 R64;
|
|
<a name="l807"></a>OPCODE CHPXCHG8B 0x0F 0xC7, RM64;
|
|
<a name="l808"></a>OPCODE DAA 0x27;
|
|
<a name="l809"></a>OPCODE DAS 0x2F;
|
|
<a name="l810"></a>OPCODE ENTER
|
|
<a name="l811"></a> 0xC8, $IW IMM16;
|
|
<a name="l812"></a>OPCODE HLT 0xF4;
|
|
<a name="l813"></a>OPCODE IN
|
|
<a name="l814"></a> 0xE4, IB &AL UIMM8
|
|
<a name="l815"></a> 0xE4, IB AL IMM8
|
|
<a name="l816"></a> 0xE5, 16 IB &AX UIMM8
|
|
<a name="l817"></a> 0xE5, 16 IB AX IMM8
|
|
<a name="l818"></a> 0xE5, 32 IB &EAX UIMM8
|
|
<a name="l819"></a> 0xE5, 32 IB EAX IMM8
|
|
<a name="l820"></a> 0xEC, AL DX
|
|
<a name="l821"></a> 0xED, 16 AX DX
|
|
<a name="l822"></a> 0xED, 32 EAX DX;
|
|
<a name="l823"></a>OPCODE INS
|
|
<a name="l824"></a> 0x6C, RM8 DX
|
|
<a name="l825"></a> 0x6D, 16 RM16 DX
|
|
<a name="l826"></a> 0x6D, 32 RM32 DX;
|
|
<a name="l827"></a>OPCODE INSB 0x6C;
|
|
<a name="l828"></a>OPCODE INSW 0x6D, 16;
|
|
<a name="l829"></a>OPCODE INSD 0x6D, 32;
|
|
<a name="l830"></a>OPCODE INTO 0xCE;
|
|
<a name="l831"></a>OPCODE INT3 0xCC, :BPT;
|
|
<a name="l832"></a>OPCODE INT
|
|
<a name="l833"></a> 0xCD, IB &UIMM8
|
|
<a name="l834"></a> 0xCD, IB IMM8;
|
|
<a name="l835"></a>OPCODE INVD 0x0F 0x08;
|
|
<a name="l836"></a>OPCODE IRET 0xCF, 32=;
|
|
<a name="l837"></a>OPCODE LAHF 0x9F;
|
|
<a name="l838"></a>OPCODE LAR
|
|
<a name="l839"></a> 0x0F 0x02,/R 16 R16 RM16
|
|
<a name="l840"></a> 0x0F 0x02,/R 32 R32 RM32
|
|
<a name="l841"></a> 0x0F 0x02,/R 32 R64 RM64;
|
|
<a name="l842"></a>OPCODE LEA
|
|
<a name="l843"></a> 0x8D,/R 16 R16 RM16
|
|
<a name="l844"></a> 0x8D,/R 32 R32 RM32
|
|
<a name="l845"></a> 0x8D,/R 32 R64 RM64;
|
|
<a name="l846"></a>OPCODE LEAVE 0xC9;
|
|
<a name="l847"></a>OPCODE LGDT
|
|
<a name="l848"></a> 0x0F 0x01,/2 16 M16
|
|
<a name="l849"></a> 0x0F 0x01,/2 32 M32
|
|
<a name="l850"></a> 0x0F 0x01,/2 32 M64;
|
|
<a name="l851"></a>OPCODE SGDT
|
|
<a name="l852"></a> 0x0F 0x01,/0 16 M16
|
|
<a name="l853"></a> 0x0F 0x01,/0 32 M32
|
|
<a name="l854"></a> 0x0F 0x01,/0 32 M64;
|
|
<a name="l855"></a>OPCODE LIDT
|
|
<a name="l856"></a> 0x0F 0x01,/3 16 M16
|
|
<a name="l857"></a> 0x0F 0x01,/3 32 M32
|
|
<a name="l858"></a> 0x0F 0x01,/3 32 M64;
|
|
<a name="l859"></a>OPCODE SIDT
|
|
<a name="l860"></a> 0x0F 0x01,/1 16 M16
|
|
<a name="l861"></a> 0x0F 0x01,/1 32 M32
|
|
<a name="l862"></a> 0x0F 0x01,/1 32 M64;
|
|
<a name="l863"></a>OPCODE LLDT
|
|
<a name="l864"></a> 0x0F 0x00,/2 RM16;
|
|
<a name="l865"></a>OPCODE SLDT
|
|
<a name="l866"></a> 0x0F 0x00,/0 16 RM16
|
|
<a name="l867"></a> 0x0F 0x00,/0 32 RM32
|
|
<a name="l868"></a> 0x0F 0x00,/0 32 RM64;
|
|
<a name="l869"></a>OPCODE LMSW
|
|
<a name="l870"></a> 0x0F 0x01,/6 RM16;
|
|
<a name="l871"></a>OPCODE SMSW
|
|
<a name="l872"></a> 0x0F 0x01,/4 16 RM16
|
|
<a name="l873"></a> 0x0F 0x01,/4 32 RM32
|
|
<a name="l874"></a> 0x0F 0x01,/4 32 RM64;
|
|
<a name="l875"></a>//OPCODE LGS LSS LFS LDS LES
|
|
<a name="l876"></a>OPCODE LOCK 0xF0;
|
|
<a name="l877"></a>OPCODE LODSB 0xAC;
|
|
<a name="l878"></a>OPCODE LODSW 0xAD, 16;
|
|
<a name="l879"></a>OPCODE LODSD 0xAD, 32;
|
|
<a name="l880"></a>OPCODE LODSQ 0xAD, 32=;
|
|
<a name="l881"></a>OPCODE LOOP 0xE2, CB REL8;
|
|
<a name="l882"></a>OPCODE LOOPE 0xE1, CB REL8 :LOOPZ;
|
|
<a name="l883"></a>OPCODE LOOPNE 0xE0, CB REL8 :LOOPNZ;
|
|
<a name="l884"></a>OPCODE LSL
|
|
<a name="l885"></a> 0x0F 0x03,/R 16 R16 RM16
|
|
<a name="l886"></a> 0x0F 0x03,/R 32 R32 RM32
|
|
<a name="l887"></a> 0x0F 0x03,/R 32 R64 RM64;
|
|
<a name="l888"></a>OPCODE LTR
|
|
<a name="l889"></a> 0x0F 0x00,/3 RM16;
|
|
<a name="l890"></a>OPCODE MOVSB 0xA4;
|
|
<a name="l891"></a>OPCODE MOVSW 0xA5, 16;
|
|
<a name="l892"></a>OPCODE MOVSD 0xA5, 32;
|
|
<a name="l893"></a>OPCODE MOVSQ 0xA5, 32=;
|
|
<a name="l894"></a>OPCODE MOVSX
|
|
<a name="l895"></a> 0x0F 0xBE,/R 16 R16 RM8
|
|
<a name="l896"></a> 0x0F 0xBE,/R 32 R32 RM8
|
|
<a name="l897"></a> 0x0F 0xBE,/R 32 R64 RM8
|
|
<a name="l898"></a> 0x0F 0xBF,/R 32 R32 RM16
|
|
<a name="l899"></a> 0x0F 0xBF,/R 32 R64 RM16;
|
|
<a name="l900"></a>OPCODE MOVSXD
|
|
<a name="l901"></a> 0x63,/R 32 R64 RM32;
|
|
<a name="l902"></a>OPCODE MOVZX
|
|
<a name="l903"></a> 0x0F 0xB6,/R 16 R16 RM8
|
|
<a name="l904"></a> 0x0F 0xB6,/R 32 R32 RM8
|
|
<a name="l905"></a> 0x0F 0xB6,/R 32 R64 RM8
|
|
<a name="l906"></a> 0x0F 0xB7,/R 32 R32 RM16
|
|
<a name="l907"></a> 0x0F 0xB7,/R 32 R64 RM16;
|
|
<a name="l908"></a>OPCODE OUT
|
|
<a name="l909"></a> 0xE6, IB &UIMM8 AL
|
|
<a name="l910"></a> 0xE6, IB IMM8 AL
|
|
<a name="l911"></a> 0xE7, 16 IB &UIMM8 AX
|
|
<a name="l912"></a> 0xE7, 16 IB IMM8 AX
|
|
<a name="l913"></a> 0xE7, 32 IB &UIMM8 EAX
|
|
<a name="l914"></a> 0xE7, 32 IB IMM8 EAX
|
|
<a name="l915"></a> 0xEE, DX AL
|
|
<a name="l916"></a> 0xEF, 16 DX AX
|
|
<a name="l917"></a> 0xEF, 32 DX EAX;
|
|
<a name="l918"></a>OPCODE OUTSB 0x6E;
|
|
<a name="l919"></a>OPCODE OUTSW 0x6F, 16;
|
|
<a name="l920"></a>OPCODE OUTSD 0x6F, 32;
|
|
<a name="l921"></a>OPCODE REP_INSB
|
|
<a name="l922"></a> 0xF3 0x6C, %
|
|
<a name="l923"></a> 0xF3 0x48 0x6C;
|
|
<a name="l924"></a>OPCODE REP_INSW 0xF3 0x6D, 16;
|
|
<a name="l925"></a>OPCODE REP_INSD 0xF3 0x6D, 32;
|
|
<a name="l926"></a>OPCODE REP_MOVSB
|
|
<a name="l927"></a> 0xF3 0xA4, %
|
|
<a name="l928"></a> 0xF3 0x48 0xA4;
|
|
<a name="l929"></a>OPCODE REP_MOVSW 0xF3 0xA5, 16;
|
|
<a name="l930"></a>OPCODE REP_MOVSD 0xF3 0xA5, 32;
|
|
<a name="l931"></a>OPCODE REP_MOVSQ 0xF3 0x48 0xA5, 32;
|
|
<a name="l932"></a>OPCODE REP_OUTSB,
|
|
<a name="l933"></a> 0xF3 0x6E, %
|
|
<a name="l934"></a> 0xF3 0x48 0x6E;
|
|
<a name="l935"></a>OPCODE REP_OUTSW 0xF3 0x6F, 16;
|
|
<a name="l936"></a>OPCODE REP_OUTSD 0xF3 0x6F, 32;
|
|
<a name="l937"></a>OPCODE REP_LODSB
|
|
<a name="l938"></a> 0xF2 0xAC, %
|
|
<a name="l939"></a> 0xF2 0x48 0xAC;
|
|
<a name="l940"></a>OPCODE REP_LODSW 0xF2 0xAD, 16;
|
|
<a name="l941"></a>OPCODE REP_LODSD 0xF2 0xAD, 32;
|
|
<a name="l942"></a>OPCODE REP_LODSQ 0xF2 0x48 0xAD, 32;
|
|
<a name="l943"></a>OPCODE REP_STOSB
|
|
<a name="l944"></a> 0xF3 0xAA, %
|
|
<a name="l945"></a> 0xF3 0x48 0xAA;
|
|
<a name="l946"></a>OPCODE REP_STOSW 0xF3 0xAB, 16;
|
|
<a name="l947"></a>OPCODE REP_STOSD 0xF3 0xAB, 32;
|
|
<a name="l948"></a>OPCODE REP_STOSQ 0xF3 0x48 0xAB, 32;
|
|
<a name="l949"></a>OPCODE REPE_CMPSB
|
|
<a name="l950"></a> 0xF3 0xA6, %
|
|
<a name="l951"></a> 0xF3 0x48 0xA6;
|
|
<a name="l952"></a>OPCODE REPE_CMPSW 0xF3 0xA7, 16;
|
|
<a name="l953"></a>OPCODE REPE_CMPSD 0xF3 0xA7, 32;
|
|
<a name="l954"></a>OPCODE REPE_CMPSQ 0xF3 0x48 0xA7, 32;
|
|
<a name="l955"></a>OPCODE REPE_SCASB
|
|
<a name="l956"></a> 0xF3 0xAE, %
|
|
<a name="l957"></a> 0xF3 0x48 0xAE;
|
|
<a name="l958"></a>OPCODE REPE_SCASW 0xF3 0xAF, 16;
|
|
<a name="l959"></a>OPCODE REPE_SCASD 0xF3 0xAF, 32;
|
|
<a name="l960"></a>OPCODE REPE_SCASQ 0xF3 0x48 0xAF, 32;
|
|
<a name="l961"></a>OPCODE REPNE_CMPSB
|
|
<a name="l962"></a> 0xF2 0xA6, %
|
|
<a name="l963"></a> 0xF2 0x48 0xA6;
|
|
<a name="l964"></a>OPCODE REPNE_CMPSW 0xF2 0xA7, 16;
|
|
<a name="l965"></a>OPCODE REPNE_CMPSD 0xF2 0xA7, 32;
|
|
<a name="l966"></a>OPCODE REPNE_CMPSQ 0xF2 0x48 0xA7, 32;
|
|
<a name="l967"></a>OPCODE REPNE_SCASB
|
|
<a name="l968"></a> 0xF2 0xAE, %
|
|
<a name="l969"></a> 0xF2 0x48 0xAE;
|
|
<a name="l970"></a>OPCODE REPNE_SCASW 0xF2 0xAF, 16;
|
|
<a name="l971"></a>OPCODE REPNE_SCASD 0xF2 0xAF, 32;
|
|
<a name="l972"></a>OPCODE REPNE_SCASQ 0xF2 0x48 0xAF, 32;
|
|
<a name="l973"></a>OPCODE RET 0xC3;
|
|
<a name="l974"></a>OPCODE RET1 0xC2, IW IMM16;
|
|
<a name="l975"></a>OPCODE RETF 0xCB;
|
|
<a name="l976"></a>OPCODE RETF1 0xCA, IW IMM16;
|
|
<a name="l977"></a>OPCODE REX 0x48;
|
|
<a name="l978"></a>OPCODE REX2 0x40;
|
|
<a name="l979"></a>OPCODE RSM 0x0F 0xAA;
|
|
<a name="l980"></a>OPCODE SAHF 0x9E;
|
|
<a name="l981"></a>OPCODE SCASB 0xAE;
|
|
<a name="l982"></a>OPCODE SCASW 0xAF, 16;
|
|
<a name="l983"></a>OPCODE SCASD 0xAF, 32;
|
|
<a name="l984"></a>OPCODE SCASQ 0xAF, 32=;
|
|
<a name="l985"></a>OPCODE SEGCS 0x2E;
|
|
<a name="l986"></a>OPCODE SEGSS 0x36;
|
|
<a name="l987"></a>OPCODE SEGDS 0x3E;
|
|
<a name="l988"></a>OPCODE SEGES 0x26;
|
|
<a name="l989"></a>OPCODE SEGFS 0x64;
|
|
<a name="l990"></a>OPCODE SEGGS 0x65;
|
|
<a name="l991"></a>OPCODE SETO 0x0F 0x90, RM8;
|
|
<a name="l992"></a>OPCODE SETNO 0x0F 0x91, RM8;
|
|
<a name="l993"></a>OPCODE SETB 0x0F 0x92, RM8 :SETC SETNAE;
|
|
<a name="l994"></a>OPCODE SETAE 0x0F 0x93, RM8 :SETNC SETNB;
|
|
<a name="l995"></a>OPCODE SETE 0x0F 0x94, RM8 :SETZ;
|
|
<a name="l996"></a>OPCODE SETNE 0x0F 0x95, RM8 :SETNZ;
|
|
<a name="l997"></a>OPCODE SETBE 0x0F 0x96, RM8 :SETNA;
|
|
<a name="l998"></a>OPCODE SETA 0x0F 0x97, RM8 :SETNBE;
|
|
<a name="l999"></a>OPCODE SETS 0x0F 0x98, RM8;
|
|
<a name="l1000"></a>OPCODE SETNS 0x0F 0x99, RM8;
|
|
<a name="l1001"></a>OPCODE SETP 0x0F 0x9A, RM8 :SETPE;
|
|
<a name="l1002"></a>OPCODE SETNP 0x0F 0x9B, RM8 :SETPO;
|
|
<a name="l1003"></a>OPCODE SETL 0x0F 0x9C, RM8 :SETNGE;
|
|
<a name="l1004"></a>OPCODE SETGE 0x0F 0x9D, RM8 :SETNL;
|
|
<a name="l1005"></a>OPCODE SETLE 0x0F 0x9E, RM8 :SETNG;
|
|
<a name="l1006"></a>OPCODE SETG 0x0F 0x9F, RM8 :SETNLE;
|
|
<a name="l1007"></a>OPCODE SHLD
|
|
<a name="l1008"></a> 0x0F 0xA5,/R 16 RM16 R16
|
|
<a name="l1009"></a> 0x0F 0xA5,/R 32 RM32 R32
|
|
<a name="l1010"></a> 0x0F 0xA5,/R 32 RM64 R64;
|
|
<a name="l1011"></a>OPCODE SHRD
|
|
<a name="l1012"></a> 0x0F 0xAD,/R 16 RM16 R16
|
|
<a name="l1013"></a> 0x0F 0xAD,/R 32 RM32 R32
|
|
<a name="l1014"></a> 0x0F 0xAD,/R 32 RM64 R64;
|
|
<a name="l1015"></a>OPCODE STC 0xF9;
|
|
<a name="l1016"></a>OPCODE STD 0xFD;
|
|
<a name="l1017"></a>OPCODE STI 0xFB;
|
|
<a name="l1018"></a>OPCODE STOSB 0xAA;
|
|
<a name="l1019"></a>OPCODE STOSW 0xAB, 16;
|
|
<a name="l1020"></a>OPCODE STOSD 0xAB, 32;
|
|
<a name="l1021"></a>OPCODE STOSQ 0xAB, 32=;
|
|
<a name="l1022"></a>OPCODE STR
|
|
<a name="l1023"></a> 0x0F 0x00,/1 16 RM16
|
|
<a name="l1024"></a> 0x0F 0x00,/1 32 RM32
|
|
<a name="l1025"></a> 0x0F 0x00,/1 32 RM64;
|
|
<a name="l1026"></a>OPCODE VERR
|
|
<a name="l1027"></a> 0x0F 0x00,/4 16 RM16
|
|
<a name="l1028"></a> 0x0F 0x00,/4 32 RM32
|
|
<a name="l1029"></a> 0x0F 0x00,/4 32 RM64;
|
|
<a name="l1030"></a>OPCODE VERW
|
|
<a name="l1031"></a> 0x0F 0x00,/5 16 RM16
|
|
<a name="l1032"></a> 0x0F 0x00,/5 32 RM32
|
|
<a name="l1033"></a> 0x0F 0x00,/5 32 RM64;
|
|
<a name="l1034"></a>OPCODE WAIT 0x9B;
|
|
<a name="l1035"></a>OPCODE FWAIT 0x9B;
|
|
<a name="l1036"></a>OPCODE XADD
|
|
<a name="l1037"></a> 0x0F 0xC0,/R RM8 R8
|
|
<a name="l1038"></a> 0x0F 0xC1,/R 16 RM16 R16
|
|
<a name="l1039"></a> 0x0F 0xC1,/R 32 RM32 R32
|
|
<a name="l1040"></a> 0x0F 0xC1,/R 32 RM64 R64;
|
|
<a name="l1041"></a>OPCODE XLATB 0xD7;
|
|
<a name="l1042"></a>
|
|
<a name="l1043"></a>OPCODE ROL
|
|
<a name="l1044"></a> 0xD2,/0 RM8 CL
|
|
<a name="l1045"></a> 0xD3,/0 16 RM16 CL
|
|
<a name="l1046"></a> 0xD3,/0 32 RM32 CL
|
|
<a name="l1047"></a> 0xD3,/0 32 RM64 CL
|
|
<a name="l1048"></a> 0xC0,/0 IB &RM8 UIMM8
|
|
<a name="l1049"></a> 0xC0,/0 IB RM8 IMM8
|
|
<a name="l1050"></a> 0xC1,/0 16 IB &RM16 UIMM8
|
|
<a name="l1051"></a> 0xC1,/0 16 IB RM16 IMM8
|
|
<a name="l1052"></a> 0xC1,/0 32 IB &RM32 UIMM8
|
|
<a name="l1053"></a> 0xC1,/0 32 IB RM32 IMM8
|
|
<a name="l1054"></a> 0xC1,/0 32 IB &RM64 UIMM8
|
|
<a name="l1055"></a> 0xC1,/0 32 IB RM64 IMM8;
|
|
<a name="l1056"></a>OPCODE ROL1
|
|
<a name="l1057"></a> 0xD0,/0 RM8
|
|
<a name="l1058"></a> 0xD1,/0 16 RM16
|
|
<a name="l1059"></a> 0xD1,/0 32 RM32
|
|
<a name="l1060"></a> 0xD1,/0 32 RM64;
|
|
<a name="l1061"></a>OPCODE ROR
|
|
<a name="l1062"></a> 0xD2,/1 RM8 CL
|
|
<a name="l1063"></a> 0xD3,/1 16 RM16 CL
|
|
<a name="l1064"></a> 0xD3,/1 32 RM32 CL
|
|
<a name="l1065"></a> 0xD3,/1 32 RM64 CL
|
|
<a name="l1066"></a> 0xC0,/1 IB &RM8 UIMM8
|
|
<a name="l1067"></a> 0xC0,/1 IB RM8 IMM8
|
|
<a name="l1068"></a> 0xC1,/1 16 IB &RM16 UIMM8
|
|
<a name="l1069"></a> 0xC1,/1 16 IB RM16 IMM8
|
|
<a name="l1070"></a> 0xC1,/1 32 IB &RM32 UIMM8
|
|
<a name="l1071"></a> 0xC1,/1 32 IB RM32 IMM8
|
|
<a name="l1072"></a> 0xC1,/1 32 IB &RM64 UIMM8
|
|
<a name="l1073"></a> 0xC1,/1 32 IB RM64 IMM8;
|
|
<a name="l1074"></a>OPCODE ROR1
|
|
<a name="l1075"></a> 0xD0,/1 RM8
|
|
<a name="l1076"></a> 0xD1,/1 16 RM16
|
|
<a name="l1077"></a> 0xD1,/1 32 RM32
|
|
<a name="l1078"></a> 0xD1,/1 32 RM64;
|
|
<a name="l1079"></a>OPCODE RCL
|
|
<a name="l1080"></a> 0xD2,/2 RM8 CL
|
|
<a name="l1081"></a> 0xD3,/2 16 RM16 CL
|
|
<a name="l1082"></a> 0xD3,/2 32 RM32 CL
|
|
<a name="l1083"></a> 0xD3,/2 32 RM64 CL
|
|
<a name="l1084"></a> 0xC0,/2 IB &RM8 UIMM8
|
|
<a name="l1085"></a> 0xC0,/2 IB RM8 IMM8
|
|
<a name="l1086"></a> 0xC1,/2 16 IB &RM16 UIMM8
|
|
<a name="l1087"></a> 0xC1,/2 16 IB RM16 IMM8
|
|
<a name="l1088"></a> 0xC1,/2 32 IB &RM32 UIMM8
|
|
<a name="l1089"></a> 0xC1,/2 32 IB RM32 IMM8
|
|
<a name="l1090"></a> 0xC1,/2 32 IB &RM64 UIMM8
|
|
<a name="l1091"></a> 0xC1,/2 32 IB RM64 IMM8;
|
|
<a name="l1092"></a>OPCODE RCL1
|
|
<a name="l1093"></a> 0xD0,/2 RM8
|
|
<a name="l1094"></a> 0xD1,/2 16 RM16
|
|
<a name="l1095"></a> 0xD1,/2 32 RM32
|
|
<a name="l1096"></a> 0xD1,/2 32 RM64;
|
|
<a name="l1097"></a>OPCODE RCR
|
|
<a name="l1098"></a> 0xD2,/3 RM8 CL
|
|
<a name="l1099"></a> 0xD3,/3 16 RM16 CL
|
|
<a name="l1100"></a> 0xD3,/3 32 RM32 CL
|
|
<a name="l1101"></a> 0xD3,/3 32 RM64 CL
|
|
<a name="l1102"></a> 0xC0,/3 IB &RM8 UIMM8
|
|
<a name="l1103"></a> 0xC0,/3 IB RM8 IMM8
|
|
<a name="l1104"></a> 0xC1,/3 16 IB &RM16 UIMM8
|
|
<a name="l1105"></a> 0xC1,/3 16 IB RM16 IMM8
|
|
<a name="l1106"></a> 0xC1,/3 32 IB &RM32 UIMM8
|
|
<a name="l1107"></a> 0xC1,/3 32 IB RM32 IMM8
|
|
<a name="l1108"></a> 0xC1,/3 32 IB &RM64 UIMM8
|
|
<a name="l1109"></a> 0xC1,/3 32 IB RM64 IMM8;
|
|
<a name="l1110"></a>OPCODE RCR1
|
|
<a name="l1111"></a> 0xD0,/3 RM8
|
|
<a name="l1112"></a> 0xD1,/3 16 RM16
|
|
<a name="l1113"></a> 0xD1,/3 32 RM32
|
|
<a name="l1114"></a> 0xD1,/3 32 RM64;
|
|
<a name="l1115"></a>OPCODE SHL
|
|
<a name="l1116"></a> 0xD2,/4 RM8 CL
|
|
<a name="l1117"></a> 0xD3,/4 16 RM16 CL
|
|
<a name="l1118"></a> 0xD3,/4 32 RM32 CL
|
|
<a name="l1119"></a> 0xD3,/4 32 RM64 CL
|
|
<a name="l1120"></a> 0xC0,/4 IB &RM8 UIMM8
|
|
<a name="l1121"></a> 0xC0,/4 IB RM8 IMM8
|
|
<a name="l1122"></a> 0xC1,/4 16 IB &RM16 UIMM8
|
|
<a name="l1123"></a> 0xC1,/4 16 IB RM16 IMM8
|
|
<a name="l1124"></a> 0xC1,/4 32 IB &RM32 UIMM8
|
|
<a name="l1125"></a> 0xC1,/4 32 IB RM32 IMM8
|
|
<a name="l1126"></a> 0xC1,/4 32 IB &RM64 UIMM8
|
|
<a name="l1127"></a> 0xC1,/4 32 IB RM64 IMM8 :SAL;
|
|
<a name="l1128"></a>OPCODE SHL1
|
|
<a name="l1129"></a> 0xD0,/4 RM8
|
|
<a name="l1130"></a> 0xD1,/4 16 RM16
|
|
<a name="l1131"></a> 0xD1,/4 32 RM32
|
|
<a name="l1132"></a> 0xD1,/4 32 RM64 :SAL1;
|
|
<a name="l1133"></a>OPCODE SHR
|
|
<a name="l1134"></a> 0xD2,/5 RM8 CL
|
|
<a name="l1135"></a> 0xD3,/5 16 RM16 CL
|
|
<a name="l1136"></a> 0xD3,/5 32 RM32 CL
|
|
<a name="l1137"></a> 0xD3,/5 32 RM64 CL
|
|
<a name="l1138"></a> 0xC0,/5 IB &RM8 UIMM8
|
|
<a name="l1139"></a> 0xC0,/5 IB RM8 IMM8
|
|
<a name="l1140"></a> 0xC1,/5 16 IB &RM16 UIMM8
|
|
<a name="l1141"></a> 0xC1,/5 16 IB RM16 IMM8
|
|
<a name="l1142"></a> 0xC1,/5 32 IB &RM32 UIMM8
|
|
<a name="l1143"></a> 0xC1,/5 32 IB RM32 IMM8
|
|
<a name="l1144"></a> 0xC1,/5 32 IB &RM64 UIMM8
|
|
<a name="l1145"></a> 0xC1,/5 32 IB RM64 IMM8;
|
|
<a name="l1146"></a>OPCODE SHR1
|
|
<a name="l1147"></a> 0xD0,/5 RM8
|
|
<a name="l1148"></a> 0xD1,/5 16 RM16
|
|
<a name="l1149"></a> 0xD1,/5 32 RM32
|
|
<a name="l1150"></a> 0xD1,/5 32 RM64;
|
|
<a name="l1151"></a>OPCODE SAR
|
|
<a name="l1152"></a> 0xD2,/7 RM8 CL
|
|
<a name="l1153"></a> 0xD3,/7 16 RM16 CL
|
|
<a name="l1154"></a> 0xD3,/7 32 RM32 CL
|
|
<a name="l1155"></a> 0xD3,/7 32 RM64 CL
|
|
<a name="l1156"></a> 0xC0,/7 IB &RM8 UIMM8
|
|
<a name="l1157"></a> 0xC0,/7 IB RM8 IMM8
|
|
<a name="l1158"></a> 0xC1,/7 16 IB &RM16 UIMM8
|
|
<a name="l1159"></a> 0xC1,/7 16 IB RM16 IMM8
|
|
<a name="l1160"></a> 0xC1,/7 32 IB &RM32 UIMM8
|
|
<a name="l1161"></a> 0xC1,/7 32 IB RM32 IMM8
|
|
<a name="l1162"></a> 0xC1,/7 32 IB &RM64 UIMM8
|
|
<a name="l1163"></a> 0xC1,/7 32 IB RM64 IMM8;
|
|
<a name="l1164"></a>OPCODE SAR1
|
|
<a name="l1165"></a> 0xD0,/7 RM8
|
|
<a name="l1166"></a> 0xD1,/7 16 RM16
|
|
<a name="l1167"></a> 0xD1,/7 32 RM32
|
|
<a name="l1168"></a> 0xD1,/7 32 RM64;
|
|
<a name="l1169"></a>
|
|
<a name="l1170"></a>OPCODE FILD
|
|
<a name="l1171"></a> 0xDF,/0 M16 //Load I16
|
|
<a name="l1172"></a> 0xDB,/0 M32 //Load I32
|
|
<a name="l1173"></a> 0xDF,/5 `M64; //Load I64
|
|
<a name="l1174"></a>OPCODE FISTP
|
|
<a name="l1175"></a> 0xDF,/7 `M64; //Store I64
|
|
<a name="l1176"></a>OPCODE FISTTP
|
|
<a name="l1177"></a> 0xDD,/1 `M64; //Store I64
|
|
<a name="l1178"></a>OPCODE FLD
|
|
<a name="l1179"></a> 0xD9,/0 M32 //Load F32
|
|
<a name="l1180"></a> 0xDD,/0 `M64 //Load F64
|
|
<a name="l1181"></a> 0xD9 0xC0,+I* STI;
|
|
<a name="l1182"></a>OPCODE FSTP
|
|
<a name="l1183"></a> 0xD9,/3 M32 //Store F32
|
|
<a name="l1184"></a> 0xDD,/3 `M64 //Store F64
|
|
<a name="l1185"></a> 0xDD 0xD8,+I* STI;
|
|
<a name="l1186"></a>OPCODE FST
|
|
<a name="l1187"></a> 0xD9,/2 M32 //Store F32
|
|
<a name="l1188"></a> 0xDD,/2 `M64 //Store F64
|
|
<a name="l1189"></a> 0xDD 0xD0,+I* STI;
|
|
<a name="l1190"></a>OPCODE FRSTOR
|
|
<a name="l1191"></a> 0xDD,/4 M32
|
|
<a name="l1192"></a> 0xDD,/4 M64;
|
|
<a name="l1193"></a>OPCODE FSAVE
|
|
<a name="l1194"></a> 0xDD,/6 M32
|
|
<a name="l1195"></a> 0xDD,/6 M64;
|
|
<a name="l1196"></a>
|
|
<a name="l1197"></a>OPCODE FYL2X 0xD9 0xF1,*;
|
|
<a name="l1198"></a>OPCODE FYL2XP1 0xD9 0xF9,*;
|
|
<a name="l1199"></a>OPCODE F2XM1 0xD9 0xF0,*;
|
|
<a name="l1200"></a>OPCODE FABS 0xD9 0xE1,*;
|
|
<a name="l1201"></a>OPCODE FCHS 0xD9 0xE0,*;
|
|
<a name="l1202"></a>OPCODE FSIN 0xD9 0xFE,*;
|
|
<a name="l1203"></a>OPCODE FCOS 0xD9 0xFF,*;
|
|
<a name="l1204"></a>OPCODE FPTAN 0xD9 0xF2,*;
|
|
<a name="l1205"></a>OPCODE FPATAN 0xD9 0xF3,*;
|
|
<a name="l1206"></a>OPCODE FSQRT 0xD9 0xFA,*;
|
|
<a name="l1207"></a>OPCODE FMULP 0xDE 0xC8,+I* STI ST0;
|
|
<a name="l1208"></a>OPCODE FMUL
|
|
<a name="l1209"></a> 0xD8,/1 ST0 M32
|
|
<a name="l1210"></a> 0xDC,/1 `ST0 M64
|
|
<a name="l1211"></a> 0xD8 0xC8,+I* ST0 STI
|
|
<a name="l1212"></a> 0xDC 0xC8,+I* STI ST0;
|
|
<a name="l1213"></a>OPCODE FIMUL
|
|
<a name="l1214"></a> 0xDA,/1 ST0 M32
|
|
<a name="l1215"></a> 0xDE,/1 ST0 M16;
|
|
<a name="l1216"></a>OPCODE FDIVP 0xDE 0xF8,+I* STI ST0;
|
|
<a name="l1217"></a>OPCODE FDIV
|
|
<a name="l1218"></a> 0xD8,/6 ST0 M32
|
|
<a name="l1219"></a> 0xDC,/6 `ST0 M64
|
|
<a name="l1220"></a> 0xD8 0xF0,+I* ST0 STI
|
|
<a name="l1221"></a> 0xDC 0xF8,+I* STI ST0;
|
|
<a name="l1222"></a>OPCODE FDIVRP 0xDE 0xF0,+I* STI ST0;
|
|
<a name="l1223"></a>OPCODE FDIVR
|
|
<a name="l1224"></a> 0xD8,/7 ST0 M32
|
|
<a name="l1225"></a> 0xDC,/7 `ST0 M64
|
|
<a name="l1226"></a> 0xD8 0xF8,+I* ST0 STI
|
|
<a name="l1227"></a> 0xDC 0xF0,+I* STI ST0;
|
|
<a name="l1228"></a>OPCODE FPREM 0xD9 0xF8,*;
|
|
<a name="l1229"></a>OPCODE FADDP 0xDE 0xC0,+I* STI ST0;
|
|
<a name="l1230"></a>OPCODE FADD
|
|
<a name="l1231"></a> 0xD8,/0 ST0 M32
|
|
<a name="l1232"></a> 0xDC,/0 `ST0 M64
|
|
<a name="l1233"></a> 0xD8 0xC0,+I* ST0 STI
|
|
<a name="l1234"></a> 0xDC 0xC0,+I* STI ST0;
|
|
<a name="l1235"></a>OPCODE FSUBP 0xDE 0xE8,+I* STI ST0;
|
|
<a name="l1236"></a>OPCODE FSUB
|
|
<a name="l1237"></a> 0xD8,/4 ST0 M32
|
|
<a name="l1238"></a> 0xDC,/4 `ST0 M64
|
|
<a name="l1239"></a> 0xD8 0xE0,+I* ST0 STI
|
|
<a name="l1240"></a> 0xDC 0xE8,+I* STI ST0;
|
|
<a name="l1241"></a>OPCODE FSUBRP 0xDE 0xE0,+I* STI ST0;
|
|
<a name="l1242"></a>OPCODE FSUBR
|
|
<a name="l1243"></a> 0xD8,/5 ST0 M32
|
|
<a name="l1244"></a> 0xDC,/5 `ST0 M64
|
|
<a name="l1245"></a> 0xD8 0xE8,+I* ST0 STI
|
|
<a name="l1246"></a> 0xDC 0xE0,+I* STI ST0;
|
|
<a name="l1247"></a>OPCODE FCOMIP 0xDF 0xF0,+I* ST0 STI;
|
|
<a name="l1248"></a>OPCODE FCOMI 0xDB 0xF0,+I* ST0 STI;
|
|
<a name="l1249"></a>OPCODE FCLEX 0x9B 0xDB 0xE2,*;
|
|
<a name="l1250"></a>OPCODE FNCLEX 0xDB 0xE2,*;
|
|
<a name="l1251"></a>OPCODE FSTSW 0xDF 0xE0,*;
|
|
<a name="l1252"></a>OPCODE FDECSTP 0xD9 0xF6,*;
|
|
<a name="l1253"></a>OPCODE FINCSTP 0xD9 0xF7,*;
|
|
<a name="l1254"></a>OPCODE FFREE 0xDD 0xC0,+I* STI;
|
|
<a name="l1255"></a>OPCODE FRNDINT 0xD9 0xFC,*;
|
|
<a name="l1256"></a>OPCODE FSCALE 0xD9 0xFD,*;
|
|
<a name="l1257"></a>OPCODE FXTRACT 0xD9 0xF4,*;
|
|
<a name="l1258"></a>
|
|
<a name="l1259"></a>OPCODE FLD1 0xD9 0xE8,*;
|
|
<a name="l1260"></a>OPCODE FLDL2T 0xD9 0xE9,*;
|
|
<a name="l1261"></a>OPCODE FLDL2E 0xD9 0xEA,*;
|
|
<a name="l1262"></a>OPCODE FLDPI 0xD9 0xEB,*;
|
|
<a name="l1263"></a>OPCODE FLDLG2 0xD9 0xEC,*;
|
|
<a name="l1264"></a>OPCODE FLDLN2 0xD9 0xED,*;
|
|
<a name="l1265"></a>OPCODE FLDZ 0xD9 0xEE,*;
|
|
<a name="l1266"></a>
|
|
<a name="l1267"></a>OPCODE FXCH 0xD9 0xC8,+I* STI;
|
|
<a name="l1268"></a>OPCODE FTST 0xD9 0xE4,*;
|
|
<a name="l1269"></a>OPCODE FXAM 0xD9 0xE5,*;
|
|
<a name="l1270"></a>OPCODE FINIT 0x9B 0xDB 0xE3;
|
|
<a name="l1271"></a>OPCODE FNINIT 0xDB 0xE3;
|
|
<a name="l1272"></a>
|
|
<a name="l1273"></a>OPCODE FSTCW
|
|
<a name="l1274"></a> 0xD9,/7 M16;
|
|
<a name="l1275"></a>OPCODE FLDCW
|
|
<a name="l1276"></a> 0xD9,/5 M16;
|
|
<a name="l1277"></a>OPCODE FXSAVE //512 byte
|
|
<a name="l1278"></a> 0x0F 0xAE,/0 32 M32
|
|
<a name="l1279"></a> 0x0F 0xAE,/0 32 M64;
|
|
<a name="l1280"></a>OPCODE FXRSTOR //512 byte
|
|
<a name="l1281"></a> 0x0F 0xAE,/1 32 M32
|
|
<a name="l1282"></a> 0x0F 0xAE,/1 32 M64;
|
|
<a name="l1283"></a>
|
|
<a name="l1284"></a>OPCODE WBINVD 0x0F 0x09;
|
|
<a name="l1285"></a>OPCODE CLFLUSH 0x0F 0xAE,/7 RM8;
|
|
<a name="l1286"></a>OPCODE INVLPG 0x0F 0x01,/7 RM8;
|
|
<a name="l1287"></a>OPCODE CPUID 0x0F 0xA2, 32=;
|
|
<a name="l1288"></a>OPCODE WRMSR 0x0F 0x30, 32=;
|
|
<a name="l1289"></a>OPCODE RDTSC 0x0F 0x31;
|
|
<a name="l1290"></a>OPCODE RDMSR 0x0F 0x32, 32=;
|
|
<a name="l1291"></a>OPCODE PAUSE 0xF3 0x90;
|
|
<a name="l1292"></a>
|
|
<a name="l1293"></a>OPCODE MOV_CR0_EAX 0x0F 0x22 0xC0;
|
|
<a name="l1294"></a>OPCODE MOV_EAX_CR0 0x0F 0x20 0xC0;
|
|
<a name="l1295"></a>OPCODE MOV_CR2_EAX 0x0F 0x22 0xD0;
|
|
<a name="l1296"></a>OPCODE MOV_EAX_CR2 0x0F 0x20 0xD0;
|
|
<a name="l1297"></a>OPCODE MOV_CR3_EAX 0x0F 0x22 0xD8;
|
|
<a name="l1298"></a>OPCODE MOV_EAX_CR3 0x0F 0x20 0xD8;
|
|
<a name="l1299"></a>OPCODE MOV_CR4_EAX 0x0F 0x22 0xE0;
|
|
<a name="l1300"></a>OPCODE MOV_EAX_CR4 0x0F 0x20 0xE0;
|
|
<a name="l1301"></a>
|
|
<a name="l1302"></a>OPCODE MOV_CR0_RAX 0x0F 0x22 0xC0, 32=;
|
|
<a name="l1303"></a>OPCODE MOV_RAX_CR0 0x0F 0x20 0xC0, 32=;
|
|
<a name="l1304"></a>OPCODE MOV_CR2_RAX 0x0F 0x22 0xD0, 32=;
|
|
<a name="l1305"></a>OPCODE MOV_RAX_CR2 0x0F 0x20 0xD0, 32=;
|
|
<a name="l1306"></a>OPCODE MOV_CR3_RAX 0x0F 0x22 0xD8, 32=;
|
|
<a name="l1307"></a>OPCODE MOV_RAX_CR3 0x0F 0x20 0xD8, 32=;
|
|
<a name="l1308"></a>OPCODE MOV_CR4_RAX 0x0F 0x22 0xE0, 32=;
|
|
<a name="l1309"></a>OPCODE MOV_RAX_CR4 0x0F 0x20 0xE0, 32=;
|
|
<a name="l1310"></a>
|
|
<a name="l1311"></a>OPCODE MULPD 0x66 0x0F 0x59,/R XMM XMM;</span></pre></body>
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</html>
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