mirror of
https://github.com/Zeal-Operating-System/ZealOS.git
synced 2025-03-13 19:45:05 +00:00
512 lines
7.2 KiB
HolyC
Executable file
512 lines
7.2 KiB
HolyC
Executable file
asm {
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//************************************
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CMP_TEMPLATES::
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DU32 @@05, @@10, @@15, @@25, @@30,
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@@35, @@40, @@45, @@55, @@60,
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@@75, @@80, @@85, @@90, @@95,
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@@100, @@105, @@110, @@120, @@130;
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@@05: //INC
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PUSH RAX
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FLD1
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FADD ST0, U64 [RSP]
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FSTP U64 [RSP]
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POP RAX
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@@10: //DEC
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PUSH RAX
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FLD1
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FSUBR ST0, U64 [RSP]
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FSTP U64 [RSP]
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POP RAX
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@@15: //MOD
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PUSH RDX
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PUSH RAX
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MOV RBX, RSP
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FLD U64 [RBX]
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FLD U64 8[RBX]
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@@20: FPREM
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FSTSW
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TEST AX, 0x400
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JNZ @@20
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FSTP U64 [RBX]
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FFREE ST0
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FINCSTP
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POP RAX
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ADD RSP, 8
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@@25: //LESS
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PUSH RDX
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PUSH RAX
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FLD U64 [RSP]
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FLD U64 8[RSP]
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FCOMIP ST0, ST1
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MOV RAX, 0
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ADC RAX, 0
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FFREE ST0
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FINCSTP
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ADD RSP, 16
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@@30: //GREATER
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PUSH RDX
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PUSH RAX
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FLD U64 8[RSP]
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 0
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ADC RAX, 0
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FFREE ST0
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FINCSTP
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ADD RSP, 16
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@@35: //LESS_EQU
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PUSH RDX
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PUSH RAX
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FLD U64 8[RSP]
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 1
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SBB RAX, 0
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FFREE ST0
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FINCSTP
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ADD RSP, 16
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@@40: //GREATER_EQU
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PUSH RDX
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PUSH RAX
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FLD U64 [RSP]
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FLD U64 8[RSP]
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FCOMIP ST0, ST1
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MOV RAX, 1
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SBB RAX, 0
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FFREE ST0
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FINCSTP
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ADD RSP, 16
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@@45: //StrLen
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MOV RDX,RAX
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@@50: MOV BL, U8 [RAX]
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INC RAX
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TEST BL, BL
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JNZ @@50
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SUB RAX, RDX
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DEC RAX
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@@55: //RDTSC
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RDTSC
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SHL RDX, 32
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ADD RAX, RDX
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@@60: //SignI64
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TEST RAX, RAX
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JZ @@70
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JS @@65
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MOV RAX, 1
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JMP @@70
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@@65: MOV RAX, -1
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@@70:
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@@75:
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@@80:
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@@85: //Sqr
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PUSH RAX
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FLD U64 [RSP]
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FMUL ST0, ST0
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FSTP U64 [RSP]
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POP RAX
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@@90: //Abs
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PUSH RAX
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FLD U64 [RSP]
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FABS
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FSTP U64 [RSP]
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POP RAX
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@@95: //Sqrt
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PUSH RAX
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FLD U64 [RSP]
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FSQRT
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FSTP U64 [RSP]
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POP RAX
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@@100: //Sin
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PUSH RAX
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FLD U64 [RSP]
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FSIN
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FSTP U64 [RSP]
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POP RAX
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@@105: //Cos
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PUSH RAX
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FLD U64 [RSP]
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FCOS
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FSTP U64 [RSP]
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POP RAX
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@@110: //Tan
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PUSH RAX
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FLD U64 [RSP]
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@@115: FPTAN
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FSTSW
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TEST AX, 0x400
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JNZ @@115
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FFREE ST0
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FINCSTP
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FSTP U64 [RSP]
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POP RAX
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@@120: //Atan
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PUSH RAX
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FLD U64 [RSP]
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FLD1
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@@125: FPATAN
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FSTSW
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TEST AX, 0x400
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JNZ @@125
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FSTP U64 [RSP]
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POP RAX
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@@130:
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//************************************
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CMP_TEMPLATES_DONT_POP::
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DU32 @@05, @@10, @@15, @@20, @@25,
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@@30, @@35, @@40, @@45, @@50,
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@@55, @@60, @@65, @@70, @@75,
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@@80, @@85, @@90, @@100, @@110;
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@@05: //INC
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PUSH RAX
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FLD1
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FADD ST0, U64 [RSP]
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FST U64 [RSP]
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POP RAX
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@@10: //DEC
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PUSH RAX
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FLD1
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FSUBR ST0, U64 [RSP]
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FST U64 [RSP]
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POP RAX
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@@15:
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@@20:
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@@25:
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@@30:
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@@35:
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@@40:
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@@45:
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@@50:
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@@55:
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@@60:
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PUSH RAX
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FLD U64 [RSP]
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ADD RSP, 8
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@@65: //Sqr
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PUSH RAX
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FLD U64 [RSP]
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FMUL ST0, ST0
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ADD RSP, 8
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@@70: //Abs
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PUSH RAX
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FLD U64 [RSP]
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FABS
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ADD RSP, 8
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@@75: //Sqrt
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PUSH RAX
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FLD U64 [RSP]
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FSQRT
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ADD RSP, 8
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@@80: //Sin
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PUSH RAX
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FLD U64 [RSP]
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FSIN
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ADD RSP, 8
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@@85: //Cos
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PUSH RAX
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FLD U64 [RSP]
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FCOS
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ADD RSP, 8
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@@90: //Tan
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PUSH RAX
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FLD U64 [RSP]
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@@95: FPTAN
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FSTSW
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TEST AX, 0x400
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JNZ @@95
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FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@100: //Atan
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PUSH RAX
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FLD U64 [RSP]
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FLD1
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@@105: FPATAN
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FSTSW
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TEST AX, 0x400
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JNZ @@105
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ADD RSP, 8
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@@110:
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//************************************
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CMP_TEMPLATES_DONT_PUSH::
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DU32 @@05, @@10, @@15, @@20, @@30,
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@@35, @@40, @@50, @@55, @@60,
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@@65, @@70, @@75, @@80, @@85,
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@@90, @@95, @@100, @@110, @@120;
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@@05: //INC
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SUB RSP, 8
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FLD1
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FADDP ST1, ST0
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FSTP U64 [RSP]
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POP RAX
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@@10: //DEC
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SUB RSP, 8
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FLD1
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FSUBP ST1, ST0
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FSTP U64 [RSP]
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POP RAX
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@@15:
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@@20: //LESS
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PUSH RAX
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 0
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JZ @@25
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MOV RAX, 1
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SBB RAX, 0
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@@25: FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@30: //GREATER
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PUSH RAX
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 0
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ADC RAX, 0
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FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@35: //LESS_EQU
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PUSH RAX
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 1
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SBB RAX, 0
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FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@40: //GREATER_EQU
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PUSH RAX
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 1
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JZ @@45
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MOV RAX, 0
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ADC RAX, 0
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@@45: FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@50:
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@@55:
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@@60:
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@@65: //FSTP
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SUB RSP, 8
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FSTP U64 [RSP]
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POP RAX
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@@70:
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@@75: //Sqr
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SUB RSP, 8
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FMUL ST0, ST0
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FSTP U64 [RSP]
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POP RAX
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@@80: //Abs
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SUB RSP, 8
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FABS
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FSTP U64 [RSP]
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POP RAX
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@@85: //Sqrt
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SUB RSP, 8
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FSQRT
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FSTP U64 [RSP]
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POP RAX
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@@90: //Sin
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SUB RSP, 8
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FSIN
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FSTP U64 [RSP]
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POP RAX
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@@95: //Cos
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SUB RSP, 8
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FCOS
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FSTP U64 [RSP]
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POP RAX
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@@100: //Tan
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SUB RSP, 8
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@@105: FPTAN
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FSTSW
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TEST AX, 0x400
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JNZ @@105
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FFREE ST0
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FINCSTP
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FSTP U64 [RSP]
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POP RAX
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@@110: //Atan
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SUB RSP, 8
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FLD1
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@@115: FPATAN
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FSTSW
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TEST AX, 0x400
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JNZ @@115
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FSTP U64 [RSP]
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POP RAX
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@@120:
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//************************************
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CMP_TEMPLATES_DONT_PUSH_POP::
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DU32 @@05, @@10, @@15, @@20, @@25,
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@@30, @@35, @@40, @@45, @@50,
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@@55, @@60, @@65, @@70, @@75,
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@@80, @@85, @@90, @@95, @@105;
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@@05: //INC
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SUB RSP, 8
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FLD1
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FADDP ST1, ST0
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FST U64 [RSP]
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POP RAX
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@@10: //DEC
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SUB RSP, 8
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FLD1
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FSUBP ST1, ST0
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FST U64 [RSP]
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POP RAX
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@@15:
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@@20:
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@@25:
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@@30:
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@@35:
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@@40:
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@@45:
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@@50:
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@@55:
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@@60:
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@@65: //Sqr
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FMUL ST0, ST0
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@@70: //Abs
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FABS
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@@75: //Sqrt
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FSQRT
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@@80: //Sin
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FSIN
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@@85: //Cos
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FCOS
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@@90: //Tan
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FPTAN
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FSTSW
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TEST AX, 0x400
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JNZ @@90
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FFREE ST0
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FINCSTP
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@@95: //Atan
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FLD1
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@@100: FPATAN
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FSTSW
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TEST AX, 0x400
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JNZ @@100
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@@105:
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//************************************
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CMP_TEMPLATES_DONT_PUSH2::
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DU32 @@05, @@10, @@15, @@20, @@25,
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@@35, @@45, @@50, @@55, @@60,
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@@65, @@70, @@75, @@80, @@85,
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@@90, @@95, @@100, @@105, @@110;
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@@05:
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@@10:
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@@15:
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@@20: //LESS
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PUSH RAX
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 0
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ADC RAX, 0
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FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@25: //GREATER
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PUSH RAX
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 0
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JZ @@30
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MOV RAX, 1
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SBB RAX, 0
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@@30: FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@35: //LESS_EQU
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PUSH RAX
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 1
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JZ @@40
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MOV RAX, 0
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ADC RAX, 0
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@@40: FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@45: //GREATER_EQU
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PUSH RAX
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FLD U64 [RSP]
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FCOMIP ST0, ST1
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MOV RAX, 1
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SBB RAX, 0
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FFREE ST0
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FINCSTP
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ADD RSP, 8
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@@50:
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@@55:
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@@60:
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@@65:
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@@70:
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@@75:
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@@80:
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@@85:
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@@90:
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@@95:
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@@100:
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@@105:
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@@110:
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}
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