/* See AsmHashLoad(). '!'= IEF_DONT_SWITCH_MODES '&'= IEF_DEFAULT '%'= IEF_NOT_IN_64_BIT Not Allowed in 64-bit. '='= IEF_48_REX Rex 0x48 only if in 64-bit mode. '`'= IEF_REX_ONLY_R8_R15 '^'= IEF_REX_XOR_LIKE '*'= IEF_STI_LIKE Floating STI-like for UAsm. '$'= IEF_ENDING_ZERO Ending zero for ENTER. Note: ZealOS uses nonstandard opcodes. Asm is kind-of a bonus and Terry made changes to make the assembler simpler. For opcodes which can have different numbers of args, he separated them out -- Like IMUL and IMUL2. The assembler will not report certain invalid forms. Get an Intel datasheet and learn which forms are valid. {Lock|Rep}{Seg|2E=NotBr|3E=Br}{OP}{ADD}{REX} ':' is start of alias list. Marked with OCF_ALIAS. */ R8 AL 0; R8 CL 1; R8 DL 2; R8 BL 3; R8 AH 4; R8 CH 5; R8 DH 6; R8 BH 7; R8 R8u8 8; R8 R9u8 9; R8 R10u8 10; R8 R11u8 11; R8 R12u8 12; R8 R13u8 13; R8 R14u8 14; R8 R15u8 15; R8 RSPu8 20; R8 RBPu8 21; R8 RSIu8 22; R8 RDIu8 23; R16 AX 0; R16 CX 1; R16 DX 2; R16 BX 3; R16 SP 4; R16 BP 5; R16 SI 6; R16 DI 7; R16 R8u16 8; R16 R9u16 9; R16 R10u16 10; R16 R11u16 11; R16 R12u16 12; R16 R13u16 13; R16 R14u16 14; R16 R15u16 15; R32 EAX 0; R32 ECX 1; R32 EDX 2; R32 EBX 3; R32 ESP 4; R32 EBP 5; R32 ESI 6; R32 EDI 7; R32 R8u32 8; R32 R9u32 9; R32 R10u32 10; R32 R11u32 11; R32 R12u32 12; R32 R13u32 13; R32 R14u32 14; R32 R15u32 15; R64 RAX 0; R64 RCX 1; R64 RDX 2; R64 RBX 3; R64 RSP 4; R64 RBP 5; R64 RSI 6; R64 RDI 7; R64 R8 8; R64 R9 9; R64 R10 10; R64 R11 11; R64 R12 12; R64 R13 13; R64 R14 14; R64 R15 15; R64 R8u64 8; R64 R9u64 9; R64 R10u64 10; R64 R11u64 11; R64 R12u64 12; R64 R13u64 13; R64 R14u64 14; R64 R15u64 15; SEG ES 0; SEG CS 1; SEG SS 2; SEG DS 3; SEG FS 4; SEG GS 5; FSTACK ST0 0; FSTACK ST1 1; FSTACK ST2 2; FSTACK ST3 3; FSTACK ST4 4; FSTACK ST5 5; FSTACK ST6 6; FSTACK ST7 7; MM MM0 0; MM MM1 1; MM MM2 2; MM MM3 3; MM MM4 4; MM MM5 5; MM MM6 6; MM MM7 7; XMM XMM0 0; XMM XMM1 1; XMM XMM2 2; XMM XMM3 3; XMM XMM4 4; XMM XMM5 5; XMM XMM6 6; XMM XMM8 8; XMM XMM9 9; XMM XMM10 10; XMM XMM11 11; XMM XMM12 12; XMM XMM13 13; XMM XMM14 14; XMM XMM15 15; KEYWORD include 0; KEYWORD define 1; KEYWORD union 2; KEYWORD catch 3; KEYWORD class 4; KEYWORD try 5; KEYWORD if 6; KEYWORD else 7; KEYWORD for 8; KEYWORD while 9; KEYWORD extern 10; KEYWORD _extern 11; KEYWORD return 12; KEYWORD sizeof 13; KEYWORD _intern 14; KEYWORD do 15; KEYWORD asm 16; KEYWORD goto 17; KEYWORD exe 18; KEYWORD break 19; KEYWORD switch 20; KEYWORD start 21; KEYWORD end 22; KEYWORD case 23; KEYWORD default 24; KEYWORD public 25; KEYWORD offset 26; KEYWORD import 27; KEYWORD _import 28; KEYWORD ifdef 29; KEYWORD ifndef 30; KEYWORD ifaot 31; KEYWORD ifjit 32; KEYWORD endif 33; KEYWORD assert 34; KEYWORD reg 35; KEYWORD noreg 36; KEYWORD lastclass 37; KEYWORD no_warn 38; KEYWORD help_index 39; KEYWORD help_file 40; KEYWORD static 41; KEYWORD lock 42; KEYWORD defined 43; KEYWORD interrupt 44; KEYWORD haserrcode 45; KEYWORD argpop 46; KEYWORD noargpop 47; ASM_KEYWORD ALIGN 64; ASM_KEYWORD ORG 65; ASM_KEYWORD I0 66; ASM_KEYWORD I8 67; ASM_KEYWORD I16 68; ASM_KEYWORD I32 69; ASM_KEYWORD I64 70; ASM_KEYWORD U0 71; ASM_KEYWORD U8 72; ASM_KEYWORD U16 73; ASM_KEYWORD U32 74; ASM_KEYWORD U64 75; ASM_KEYWORD F64 76; ASM_KEYWORD DU8 77; ASM_KEYWORD DU16 78; ASM_KEYWORD DU32 79; ASM_KEYWORD DU64 80; ASM_KEYWORD DUP 81; ASM_KEYWORD USE16 82; ASM_KEYWORD USE32 83; ASM_KEYWORD USE64 84; ASM_KEYWORD IMPORT 85; ASM_KEYWORD LIST 86; ASM_KEYWORD NOLIST 87; ASM_KEYWORD BINFILE 88; OPCODE PUSH 0x0E, CS 0x16, SS 0x1E, DS 0x06, ES 0x0F 0xA0, FS 0x0F 0xA8, GS 0x6A, &IB IMM8 0x68, 16 !IW IMM16 0x68, 32 !ID IMM32 0x50,+R 16 % R16 0x50,+R 32 R32 0x50,+R 32 `R64 0xFF,/6 16 % RM16 0xFF,/6 32 RM32 0xFF,/6 32 RM64; OPCODE PUSHA 0x60, 16; OPCODE PUSHAD 0x60, 32; OPCODE PUSHF 0x9C, 16; OPCODE PUSHFD 0x9C, 32; OPCODE POP 0x1F, DS 0x07, ES 0x17, SS 0x0F 0xA1, FS 0x0F 0xA9, GS 0x58,+R 16 R16 0x58,+R 32 R32 0x58,+R 32 `R64 0x8F,/0 16 RM16 0x8F,/0 32 RM32 0x8F,/0 32 RM64; OPCODE POPA 0x61, 16; OPCODE POPAD 0x61, 32; OPCODE POPF 0x9D, 16; OPCODE POPFD 0x9D, 32; OPCODE MOV // 0xA0, AL MOFFS8 0xA1, 16 AX MOFFS16 0xA1, 32 EAX MOFFS32 // 0xA2, MOFFS8 AL 0xA3, 16 MOFFS16 AX 0xA3, 32 MOFFS32 EAX 0x8A,/R R8 RM8 0x8B,/R 16 R16 RM16 0x8B,/R 32 R32 RM32 0x8B,/R 32 R64 RM64 0x88,/R RM8 R8 0x89,/R 16 RM16 R16 0x89,/R 32 RM32 R32 0x89,/R 32 RM64 R64 0x8C,/R 32 RM16 SREG 0x8E,/R 32 SREG RM16 0xB0,+R &R8 UIMM8 0xB0,+R R8 IMM8 0xB8,+R 16 &R16 UIMM16 0xB8,+R 16 R16 IMM16 0xB8,+R 32 &R32 UIMM32 0xB8,+R 32 R32 IMM32 0xB8,+R 32 `R64 UIMM32 0xB8,+R 32 &R64 UIMM64 0xB8,+R 32 R64 IMM64 0xC6, &RM8 UIMM8 0xC6, RM8 IMM8 0xC7, 16 &RM16 UIMM16 0xC7, 16 RM16 IMM16 0xC7, 32 &RM32 UIMM32 0xC7, 32 RM32 IMM32 0xC7, 32 `RM64 UIMM32 0xC7, 32 RM64 IMM32; OPCODE ADC 0x14, IB &AL UIMM8 0x14, IB AL IMM8 0x15, 16 IW &AX UIMM16 0x15, 16 IW AX IMM16 0x15, 32 ID &EAX UIMM32 0x15, 32 ID EAX IMM32 0x80,/2 IB RM8 IMM8 0x83,/2 16 IB RM16 IMM8 0x83,/2 32 IB RM32 IMM8 0x83,/2 32 IB RM64 IMM8 0x81,/2 16 IW RM16 IMM16 0x81,/2 32 ID RM32 IMM32 0x81,/2 32 ID RM64 IMM32 0x12,/R R8 RM8 0x13,/R 16 R16 RM16 0x13,/R 32 R32 RM32 0x13,/R 32 R64 RM64 0x10,/R RM8 R8 0x11,/R 16 RM16 R16 0x11,/R 32 RM32 R32 0x11,/R 32 RM64 R64; OPCODE ADD 0x04, IB &AL UIMM8 0x04, IB AL IMM8 0x05, 16 IW &AX UIMM16 0x05, 16 IW AX IMM16 0x05, 32 ID &EAX UIMM32 0x05, 32 ID EAX IMM32 0x80,/0 IB &RM8 UIMM8 0x80,/0 IB RM8 IMM8 0x83,/0 16 IB RM16 IMM8 0x83,/0 32 IB RM32 IMM8 0x83,/0 32 IB RM64 IMM8 0x81,/0 16 IW RM16 IMM16 0x81,/0 32 ID RM32 IMM32 0x81,/0 32 ID RM64 IMM32 0x02,/R R8 RM8 0x03,/R 16 R16 RM16 0x03,/R 32 R32 RM32 0x03,/R 32 R64 RM64 0x00,/R RM8 R8 0x01,/R 16 RM16 R16 0x01,/R 32 RM32 R32 0x01,/R 32 RM64 R64; OPCODE AND 0x24, IB &AL UIMM8 0x24, IB AL IMM8 0x25, 16 IW &AX UIMM16 0x25, 16 IW AX IMM16 0x25, 32 ID &EAX UIMM32 0x25, 32 ID EAX IMM32 0x80,/4 IB &RM8 UIMM8 0x80,/4 IB RM8 IMM8 0x83,/4 16 IB RM16 IMM8 0x83,/4 32 IB RM32 IMM8 0x83,/4 32 IB RM64 IMM8 0x81,/4 16 IW RM16 IMM16 0x81,/4 32 ID RM32 IMM32 0x81,/4 32 ID RM64 IMM32 0x22,/R R8 RM8 0x23,/R 16 R16 RM16 0x23,/R 32 R32 RM32 0x23,/R 32 R64 RM64 0x20,/R RM8 R8 0x21,/R 16 RM16 R16 0x21,/R 32 RM32 R32 0x21,/R 32 RM64 R64; OPCODE CMP 0x3C, IB &AL UIMM8 0x3C, IB AL IMM8 0x3D, 16 IW &AX UIMM16 0x3D, 16 IW AX IMM16 0x3D, 32 ID &EAX UIMM32 0x3D, 32 ID EAX IMM32 0x80,/7 IB &RM8 UIMM8 0x80,/7 IB RM8 IMM8 0x83,/7 16 IB RM16 IMM8 0x83,/7 32 IB RM32 IMM8 0x83,/7 32 IB RM64 IMM8 0x81,/7 16 IW RM16 IMM16 0x81,/7 32 ID RM32 IMM32 0x81,/7 32 ID RM64 IMM32 0x3A,/R R8 RM8 0x3B,/R 16 R16 RM16 //ERROR? 0x3B,/R 32 R32 RM32 0x3B,/R 32 R64 RM64 0x38,/R RM8 R8 0x39,/R 16 RM16 R16 0x39,/R 32 RM32 R32 0x39,/R 32 RM64 R64; OPCODE OR 0x0C, IB &AL UIMM8 0x0C, IB AL IMM8 0x0D, 16 IW &AX UIMM16 0x0D, 16 IW AX IMM16 0x0D, 32 ID &EAX UIMM32 0x0D, 32 ID EAX IMM32 0x80,/1 IB &RM8 UIMM8 0x80,/1 IB RM8 IMM8 0x83,/1 16 IB RM16 IMM8 0x83,/1 32 IB RM32 IMM8 0x83,/1 32 IB RM64 IMM8 0x81,/1 16 IW RM16 IMM16 0x81,/1 32 ID RM32 IMM32 0x81,/1 32 ID RM64 IMM32 0x0A,/R R8 RM8 0x0B,/R 16 R16 RM16 0x0B,/R 32 R32 RM32 0x0B,/R 32 R64 RM64 0x08,/R RM8 R8 0x09,/R 16 RM16 R16 0x09,/R 32 RM32 R32 0x09,/R 32 RM64 R64; OPCODE SBB 0x1C, IB &AL UIMM8 0x1C, IB AL IMM8 0x1D, 16 IW &AX UIMM16 0x1D, 16 IW AX IMM16 0x1D, 32 ID &EAX UIMM32 0x1D, 32 ID EAX IMM32 0x80,/3 IB &RM8 UIMM8 0x80,/3 IB RM8 IMM8 0x83,/3 16 IB RM16 IMM8 0x83,/3 32 IB RM32 IMM8 0x83,/3 32 IB RM64 IMM8 0x81,/3 16 IW RM16 IMM16 0x81,/3 32 ID RM32 IMM32 0x81,/3 32 ID RM64 IMM32 0x1A,/R R8 RM8 0x1B,/R 16 R16 RM16 0x1B,/R 32 R32 RM32 0x1B,/R 32 R64 RM64 0x18,/R RM8 R8 0x19,/R 16 RM16 R16 0x19,/R 32 RM32 R32 0x19,/R 32 RM64 R64; OPCODE SUB 0x2C, IB &AL UIMM8 0x2C, IB AL IMM8 0x2D, 16 IW &AX UIMM16 0x2D, 16 IW AX IMM16 0x2D, 32 ID &EAX UIMM32 0x2D, 32 ID EAX IMM32 0x80,/5 IB &RM8 UIMM8 0x80,/5 IB RM8 IMM8 0x83,/5 16 IB RM16 IMM8 0x83,/5 32 IB RM32 IMM8 0x83,/5 32 IB RM64 IMM8 0x81,/5 16 IW RM16 IMM16 0x81,/5 32 ID RM32 IMM32 0x81,/5 32 ID RM64 IMM32 0x2A,/R R8 RM8 0x2B,/R 16 R16 RM16 0x2B,/R 32 R32 RM32 0x2B,/R 32 R64 RM64 0x28,/R RM8 R8 0x29,/R 16 RM16 R16 0x29,/R 32 RM32 R32 0x29,/R 32 RM64 R64; OPCODE TEST 0xA8, IB &AL UIMM8 0xA8, IB AL IMM8 0xA9, 16 IW &AX UIMM16 0xA9, 16 IW AX IMM16 0xA9, 32 ID &EAX UIMM32 0xA9, 32 ID EAX IMM32 0xF6,/0 IB &RM8 UIMM8 0xF6,/0 IB RM8 IMM8 0xF7,/0 16 IW RM16 IMM16 0xF7,/0 32 ID RM32 IMM32 0xF7,/0 32 ID RM64 IMM32 0x84,/R RM8 R8 0x85,/R 16 RM16 R16 0x85,/R 32 RM32 R32 0x85,/R 32 RM64 R64; OPCODE NOP 0x90; OPCODE NOP2 0x66 0x90; OPCODE XCHG 0x90,+R 16 R16 AX 0x90,+R 16 AX R16 0x90,+R 32 R32 EAX 0x90,+R 32 EAX R32 0x90,+R 32 R64 RAX 0x90,+R 32 RAX R64 0x86,/R R8 RM8 0x87,/R 16 R16 RM16 0x87,/R 32 R32 RM32 0x87,/R 32 R64 RM64 0x86,/R RM8 R8 0x87,/R 16 RM16 R16 0x87,/R 32 RM32 R32 0x87,/R 32 RM64 R64; OPCODE XOR 0x34, IB &AL UIMM8 0x34, IB AL IMM8 0x35, 16 IW &AX UIMM16 0x35, 16 IW AX IMM16 0x35, 32 ID &EAX UIMM32 0x35, 32 ID EAX IMM32 0x80,/6 IB &RM8 UIMM8 0x80,/6 IB RM8 IMM8 0x83,/6 16 IB RM16 IMM8 0x83,/6 32 IB RM32 IMM8 0x83,/6 32 IB RM64 IMM8 0x81,/6 16 IW RM16 IMM16 0x81,/6 32 ID RM32 IMM32 0x81,/6 32 ID RM64 IMM32 0x32,/R R8 RM8 0x33,/R 16 R16 RM16 0x33,/R 32 R32 RM32 0x33,/R 32 ^ R64 RM64 0x30,/R RM8 R8 0x31,/R 16 RM16 R16 0x31,/R 32 RM32 R32 0x31,/R 32 ^ RM64 R64; OPCODE CMOVO 0x0F 0x40,/R 16 R16 RM16 0x0F 0x40,/R 32 R32 RM32 0x0F 0x40,/R 32 R64 RM64; OPCODE CMOVNO 0x0F 0x41,/R 16 R16 RM16 0x0F 0x41,/R 32 R32 RM32 0x0F 0x41,/R 32 R64 RM64; OPCODE CMOVB 0x0F 0x42,/R 16 R16 RM16 0x0F 0x42,/R 32 R32 RM32 0x0F 0x42,/R 32 R64 RM64 :CMOVC CMOVNAE; OPCODE CMOVAE 0x0F 0x43,/R 16 R16 RM16 0x0F 0x43,/R 32 R32 RM32 0x0F 0x43,/R 32 R64 RM64 :CMOVNB CMOVNC; OPCODE CMOVE 0x0F 0x44,/R 16 R16 RM16 0x0F 0x44,/R 32 R32 RM32 0x0F 0x44,/R 32 R64 RM64 :CMOVZ; OPCODE CMOVNE 0x0F 0x45,/R 16 R16 RM16 0x0F 0x45,/R 32 R32 RM32 0x0F 0x45,/R 32 R64 RM64 :CMOVNZ; OPCODE CMOVBE 0x0F 0x46,/R 16 R16 RM16 0x0F 0x46,/R 32 R32 RM32 0x0F 0x46,/R 32 R64 RM64 :CMOVNA; OPCODE CMOVA 0x0F 0x47,/R 16 R16 RM16 0x0F 0x47,/R 32 R32 RM32 0x0F 0x47,/R 32 R64 RM64 :CMOVNBE; OPCODE CMOVS 0x0F 0x48,/R 16 R16 RM16 0x0F 0x48,/R 32 R32 RM32 0x0F 0x48,/R 32 R64 RM64; OPCODE CMOVNS 0x0F 0x49,/R 16 R16 RM16 0x0F 0x49,/R 32 R32 RM32 0x0F 0x49,/R 32 R64 RM64; OPCODE CMOVP 0x0F 0x4A,/R 16 R16 RM16 0x0F 0x4A,/R 32 R32 RM32 0x0F 0x4A,/R 32 R64 RM64 :CMOVPE; OPCODE CMOVNP 0x0F 0x4B,/R 16 R16 RM16 0x0F 0x4B,/R 32 R32 RM32 0x0F 0x4B,/R 32 R64 RM64 :CMOVPO; OPCODE CMOVL 0x0F 0x4C,/R 16 R16 RM16 0x0F 0x4C,/R 32 R32 RM32 0x0F 0x4C,/R 32 R64 RM64 :CMOVNGE; OPCODE CMOVGE 0x0F 0x4D,/R 16 R16 RM16 0x0F 0x4D,/R 32 R32 RM32 0x0F 0x4D,/R 32 R64 RM64 :CMOVNL; OPCODE CMOVLE 0x0F 0x4E,/R 16 R16 RM16 0x0F 0x4E,/R 32 R32 RM32 0x0F 0x4E,/R 32 R64 RM64 :CMOVNG; OPCODE CMOVG 0x0F 0x4F,/R 16 R16 RM16 0x0F 0x4F,/R 32 R32 RM32 0x0F 0x4F,/R 32 R64 RM64 :CMOVNLE; OPCODE CALL 0xE8, 16 !&CW REL16 0xFF,/2 16 ! RM16 0xE8, 32 !&CD REL32 0xFF,/2 32 ! RM32 0xFF,/2 32 !`RM64 // 0x9A, CD PTR1616 // 0xFF,/3 16 M1616 // 0x9A, 16 CP PTR1632 // 0x9A, 32 CP PTR3232 // 0xFF,/3 32 M1632 ; OPCODE JMP 0xEB, &CB REL8 0xE9, 16 !CW REL16 0xE9, 32 !CD REL32 0xFF,/4 16 ! RM16 0xFF,/4 32 ! RM32 0xFF,/4 32 ! RM64; OPCODE JO 0x70, &CB REL8 0x0F 0x80, 16 !CW REL16 0x0F 0x80, 32 !CD REL32; OPCODE JNO 0x71, &CB REL8 0x0F 0x81, 16 !CW REL16 0x0F 0x81, 32 !CD REL32; OPCODE JB 0x72, &CB REL8 0x0F 0x82, 16 !CW REL16 0x0F 0x82, 32 !CD REL32 :JC JNAE; OPCODE JAE 0x73, &CB REL8 0x0F 0x83, 16 !CW REL16 0x0F 0x83, 32 !CD REL32 :JNB JNC; OPCODE JE 0x74, &CB REL8 0x0F 0x84, 16 !CW REL16 0x0F 0x84, 32 !CD REL32 :JZ; OPCODE JNE 0x75, &CB REL8 0x0F 0x85, 16 !CW REL16 0x0F 0x85, 32 !CD REL32 :JNZ; OPCODE JBE 0x76, &CB REL8 0x0F 0x86, 16 !CW REL16 0x0F 0x86, 32 !CD REL32 :JNA; OPCODE JA 0x77, &CB REL8 0x0F 0x87, 16 !CW REL16 0x0F 0x87, 32 !CD REL32 :JNBE; OPCODE JS 0x78, &CB REL8 0x0F 0x88, 16 !CW REL16 0x0F 0x88, 32 !CD REL32; OPCODE JNS 0x79, &CB REL8 0x0F 0x89, 16 !CW REL16 0x0F 0x89, 32 !CD REL32; OPCODE JP 0x7A, &CB REL8 0x0F 0x8A, 16 !CW REL16 0x0F 0x8A, 32 !CD REL32 :JPE; OPCODE JNP 0x7B, &CB REL8 0x0F 0x8B, 16 !CW REL16 0x0F 0x8B, 32 !CD REL32 :JPO; OPCODE JL 0x7C, &CB REL8 0x0F 0x8C, 16 !CW REL16 0x0F 0x8C, 32 !CD REL32 :JNGE; OPCODE JGE 0x7D, &CB REL8 0x0F 0x8D, 16 !CW REL16 0x0F 0x8D, 32 !CD REL32 :JNL; OPCODE JLE 0x7E, &CB REL8 0x0F 0x8E, 16 !CW REL16 0x0F 0x8E, 32 !CD REL32 :JNG; OPCODE JG 0x7F, &CB REL8 0x0F 0x8F, 16 !CW REL16 0x0F 0x8F, 32 !CD REL32 :JNLE; OPCODE JCXZ 0xE3, CB REL8 :JECXZ JRCXZ; OPCODE INC 0x40,+R 16 % R16 0x40,+R 32 % R32 0xFE,/0 RM8 0xFF,/0 16 RM16 0xFF,/0 32 RM32 0xFF,/0 32 RM64; OPCODE DEC 0x48,+R 16 % R16 0x48,+R 32 % R32 0xFE,/1 RM8 0xFF,/1 16 RM16 0xFF,/1 32 RM32 0xFF,/1 32 RM64; OPCODE NOT 0xF6,/2 RM8 0xF7,/2 16 RM16 0xF7,/2 32 RM32 0xF7,/2 32 RM64; OPCODE NEG 0xF6,/3 RM8 0xF7,/3 16 RM16 0xF7,/3 32 RM32 0xF7,/3 32 RM64; OPCODE MUL 0xF6,/4 RM8 0xF7,/4 16 RM16 0xF7,/4 32 RM32 0xF7,/4 32 RM64; OPCODE IMUL 0xF6,/5 RM8 0xF7,/5 16 RM16 0xF7,/5 32 RM32 0xF7,/5 32 RM64; OPCODE IMUL2 0x0F 0xAF,/R 16 R16 RM16 0x0F 0xAF,/R 32 R32 RM32 0x0F 0xAF,/R 32 R64 RM64 0x6B,/R 16 IB RM16 IMM8 0x6B,/R 32 IB RM32 IMM8 0x6B,/R 32 IB RM64 IMM8 0x69,/R 16 IW &RM16 UIMM16 0x69,/R 16 IW RM16 IMM16 0x69,/R 32 ID &RM32 UIMM32 0x69,/R 32 ID RM32 IMM32 0x69,/R 32 ID &RM64 UIMM32 0x69,/R 32 ID RM64 IMM32; OPCODE DIV 0xF6,/6 RM8 0xF7,/6 16 RM16 0xF7,/6 32 RM32 0xF7,/6 32 RM64; OPCODE IDIV 0xF6,/7 RM8 0xF7,/7 16 RM16 0xF7,/7 32 RM32 0xF7,/7 32 RM64; OPCODE AAA 0x37; OPCODE AAD 0xD5 0x0A; OPCODE AAM 0xD4 0x0A; OPCODE AAS 0x3F; OPCODE ARPL 0x63,/R RM16 R16; OPCODE BOUND 0x62,/R 16 RM16 R16 0x62,/R 32 RM32 R32 0x62,/R 32 RM64 R64; OPCODE BSF 0x0F 0xBC,/R 16 R16 RM16 0x0F 0xBC,/R 32 R32 RM32 0x0F 0xBC,/R 32 R64 RM64; OPCODE BSR 0x0F 0xBD,/R 16 R16 RM16 0x0F 0xBD,/R 32 R32 RM32 0x0F 0xBD,/R 32 R64 RM64; OPCODE BSWAP 0x0F 0xC8,/R 32 R32 0x0F 0xC8,/R 32 R64; OPCODE BT 0x0F 0xA3,/R 16 RM16 R16 0x0F 0xA3,/R 32 RM32 R32 0x0F 0xA3,/R 32 RM64 R64 0x0F 0xBA,/4 16 IB &RM16 UIMM8 0x0F 0xBA,/4 16 IB RM16 IMM8 0x0F 0xBA,/4 32 IB &RM32 UIMM8 0x0F 0xBA,/4 32 IB RM32 IMM8 0x0F 0xBA,/4 32 IB &RM64 UIMM8 0x0F 0xBA,/4 32 IB RM64 IMM8; OPCODE BTC 0x0F 0xBB,/R 16 RM16 R16 0x0F 0xBB,/R 32 RM32 R32 0x0F 0xBB,/R 32 RM64 R64 0x0F 0xBA,/7 16 IB &RM16 UIMM8 0x0F 0xBA,/7 16 IB RM16 IMM8 0x0F 0xBA,/7 32 IB &RM32 UIMM8 0x0F 0xBA,/7 32 IB RM32 IMM8 0x0F 0xBA,/7 32 IB &RM64 UIMM8 0x0F 0xBA,/7 32 IB RM64 IMM8; OPCODE BTR 0x0F 0xB3,/R 16 RM16 R16 0x0F 0xB3,/R 32 RM32 R32 0x0F 0xB3,/R 32 RM64 R64 0x0F 0xBA,/6 16 IB &RM16 UIMM8 0x0F 0xBA,/6 16 IB RM16 IMM8 0x0F 0xBA,/6 32 IB &RM32 UIMM8 0x0F 0xBA,/6 32 IB RM32 IMM8 0x0F 0xBA,/6 32 IB &RM64 UIMM8 0x0F 0xBA,/6 32 IB RM64 IMM8; OPCODE BTS 0x0F 0xAB,/R 16 RM16 R16 0x0F 0xAB,/R 32 RM32 R32 0x0F 0xAB,/R 32 RM64 R64 0x0F 0xBA,/5 16 IB &RM16 UIMM8 0x0F 0xBA,/5 16 IB RM16 IMM8 0x0F 0xBA,/5 32 IB &RM32 UIMM8 0x0F 0xBA,/5 32 IB RM32 IMM8 0x0F 0xBA,/5 32 IB &RM64 UIMM8 0x0F 0xBA,/5 32 IB RM64 IMM8; OPCODE POPCNT 0xF3 0x0F 0xB8,/R 16 R16 RM16 0xF3 0x0F 0xB8,/R 32 R32 RM32 0xF3 0x48 0x0F 0xB8,/R 32 R64 RM64; OPCODE CBW 0x98, 16; OPCODE CWDE 0x98, 32; OPCODE CDQE 0x98, 32=; OPCODE CWD 0x99, 16; OPCODE CDQ 0x99, 32; OPCODE CQO 0x99, 32=; OPCODE CLC 0xF8; OPCODE CLD 0xFC; OPCODE CLI 0xFA; OPCODE CLTS 0x0F 0x06; OPCODE CMC 0xF5; OPCODE CMPSB 0xA6; OPCODE CMPSW 0xA7, 16; OPCODE CMPSD 0xA7, 32; OPCODE CMPSQ 0xA7, 32=; OPCODE CMPXCHG 0x0F 0xB0,/R RM8 R8 0x0F 0xB1,/R 16 RM16 R16 0x0F 0xB1,/R 32 RM32 R32 0x0F 0xB1,/R 32 RM64 R64; OPCODE CHPXCHG8B 0x0F 0xC7, RM64; OPCODE DAA 0x27; OPCODE DAS 0x2F; OPCODE ENTER 0xC8, $IW IMM16; OPCODE HLT 0xF4; OPCODE IN 0xE4, IB &AL UIMM8 0xE4, IB AL IMM8 0xE5, 16 IB &AX UIMM8 0xE5, 16 IB AX IMM8 0xE5, 32 IB &EAX UIMM8 0xE5, 32 IB EAX IMM8 0xEC, AL DX 0xED, 16 AX DX 0xED, 32 EAX DX; OPCODE INS 0x6C, RM8 DX 0x6D, 16 RM16 DX 0x6D, 32 RM32 DX; OPCODE INSB 0x6C; OPCODE INSW 0x6D, 16; OPCODE INSD 0x6D, 32; OPCODE INTO 0xCE; OPCODE INT3 0xCC, :BPT; OPCODE INT 0xCD, IB &UIMM8 0xCD, IB IMM8; OPCODE INVD 0x0F 0x08; OPCODE IRET 0xCF, 32=; OPCODE LAHF 0x9F; OPCODE LAR 0x0F 0x02,/R 16 R16 RM16 0x0F 0x02,/R 32 R32 RM32 0x0F 0x02,/R 32 R64 RM64; OPCODE LEA 0x8D,/R 16 R16 RM16 0x8D,/R 32 R32 RM32 0x8D,/R 32 R64 RM64; OPCODE LEAVE 0xC9; OPCODE LGDT 0x0F 0x01,/2 16 M16 0x0F 0x01,/2 32 M32 0x0F 0x01,/2 32 M64; OPCODE SGDT 0x0F 0x01,/0 16 M16 0x0F 0x01,/0 32 M32 0x0F 0x01,/0 32 M64; OPCODE LIDT 0x0F 0x01,/3 16 M16 0x0F 0x01,/3 32 M32 0x0F 0x01,/3 32 M64; OPCODE SIDT 0x0F 0x01,/1 16 M16 0x0F 0x01,/1 32 M32 0x0F 0x01,/1 32 M64; OPCODE LLDT 0x0F 0x00,/2 RM16; OPCODE SLDT 0x0F 0x00,/0 16 RM16 0x0F 0x00,/0 32 RM32 0x0F 0x00,/0 32 RM64; OPCODE LMSW 0x0F 0x01,/6 RM16; OPCODE SMSW 0x0F 0x01,/4 16 RM16 0x0F 0x01,/4 32 RM32 0x0F 0x01,/4 32 RM64; //OPCODE LGS LSS LFS LDS LES OPCODE LOCK 0xF0; OPCODE LODSB 0xAC; OPCODE LODSW 0xAD, 16; OPCODE LODSD 0xAD, 32; OPCODE LODSQ 0xAD, 32=; OPCODE LOOP 0xE2, CB REL8; OPCODE LOOPE 0xE1, CB REL8 :LOOPZ; OPCODE LOOPNE 0xE0, CB REL8 :LOOPNZ; OPCODE LSL 0x0F 0x03,/R 16 R16 RM16 0x0F 0x03,/R 32 R32 RM32 0x0F 0x03,/R 32 R64 RM64; OPCODE LTR 0x0F 0x00,/3 RM16; OPCODE MOVSB 0xA4; OPCODE MOVSW 0xA5, 16; OPCODE MOVSD 0xA5, 32; OPCODE MOVSQ 0xA5, 32=; OPCODE MOVSX 0x0F 0xBE,/R 16 R16 RM8 0x0F 0xBE,/R 32 R32 RM8 0x0F 0xBE,/R 32 R64 RM8 0x0F 0xBF,/R 32 R32 RM16 0x0F 0xBF,/R 32 R64 RM16; OPCODE MOVSXD 0x63,/R 32 R64 RM32; OPCODE MOVZX 0x0F 0xB6,/R 16 R16 RM8 0x0F 0xB6,/R 32 R32 RM8 0x0F 0xB6,/R 32 R64 RM8 0x0F 0xB7,/R 32 R32 RM16 0x0F 0xB7,/R 32 R64 RM16; OPCODE OUT 0xE6, IB &UIMM8 AL 0xE6, IB IMM8 AL 0xE7, 16 IB &UIMM8 AX 0xE7, 16 IB IMM8 AX 0xE7, 32 IB &UIMM8 EAX 0xE7, 32 IB IMM8 EAX 0xEE, DX AL 0xEF, 16 DX AX 0xEF, 32 DX EAX; OPCODE OUTSB 0x6E; OPCODE OUTSW 0x6F, 16; OPCODE OUTSD 0x6F, 32; OPCODE REP_INSB 0xF3 0x6C, % 0xF3 0x48 0x6C; OPCODE REP_INSW 0xF3 0x6D, 16; OPCODE REP_INSD 0xF3 0x6D, 32; OPCODE REP_MOVSB 0xF3 0xA4, % 0xF3 0x48 0xA4; OPCODE REP_MOVSW 0xF3 0xA5, 16; OPCODE REP_MOVSD 0xF3 0xA5, 32; OPCODE REP_MOVSQ 0xF3 0x48 0xA5, 32; OPCODE REP_OUTSB, 0xF3 0x6E, % 0xF3 0x48 0x6E; OPCODE REP_OUTSW 0xF3 0x6F, 16; OPCODE REP_OUTSD 0xF3 0x6F, 32; OPCODE REP_LODSB 0xF2 0xAC, % 0xF2 0x48 0xAC; OPCODE REP_LODSW 0xF2 0xAD, 16; OPCODE REP_LODSD 0xF2 0xAD, 32; OPCODE REP_LODSQ 0xF2 0x48 0xAD, 32; OPCODE REP_STOSB 0xF3 0xAA, % 0xF3 0x48 0xAA; OPCODE REP_STOSW 0xF3 0xAB, 16; OPCODE REP_STOSD 0xF3 0xAB, 32; OPCODE REP_STOSQ 0xF3 0x48 0xAB, 32; OPCODE REPE_CMPSB 0xF3 0xA6, % 0xF3 0x48 0xA6; OPCODE REPE_CMPSW 0xF3 0xA7, 16; OPCODE REPE_CMPSD 0xF3 0xA7, 32; OPCODE REPE_CMPSQ 0xF3 0x48 0xA7, 32; OPCODE REPE_SCASB 0xF3 0xAE, % 0xF3 0x48 0xAE; OPCODE REPE_SCASW 0xF3 0xAF, 16; OPCODE REPE_SCASD 0xF3 0xAF, 32; OPCODE REPE_SCASQ 0xF3 0x48 0xAF, 32; OPCODE REPNE_CMPSB 0xF2 0xA6, % 0xF2 0x48 0xA6; OPCODE REPNE_CMPSW 0xF2 0xA7, 16; OPCODE REPNE_CMPSD 0xF2 0xA7, 32; OPCODE REPNE_CMPSQ 0xF2 0x48 0xA7, 32; OPCODE REPNE_SCASB 0xF2 0xAE, % 0xF2 0x48 0xAE; OPCODE REPNE_SCASW 0xF2 0xAF, 16; OPCODE REPNE_SCASD 0xF2 0xAF, 32; OPCODE REPNE_SCASQ 0xF2 0x48 0xAF, 32; OPCODE RET 0xC3; OPCODE RET1 0xC2, IW IMM16; OPCODE RETF 0xCB; OPCODE RETF1 0xCA, IW IMM16; OPCODE REX 0x48; OPCODE REX2 0x40; OPCODE RSM 0x0F 0xAA; OPCODE SAHF 0x9E; OPCODE SCASB 0xAE; OPCODE SCASW 0xAF, 16; OPCODE SCASD 0xAF, 32; OPCODE SCASQ 0xAF, 32=; OPCODE SEGCS 0x2E; OPCODE SEGSS 0x36; OPCODE SEGDS 0x3E; OPCODE SEGES 0x26; OPCODE SEGFS 0x64; OPCODE SEGGS 0x65; OPCODE SETO 0x0F 0x90, RM8; OPCODE SETNO 0x0F 0x91, RM8; OPCODE SETB 0x0F 0x92, RM8 :SETC SETNAE; OPCODE SETAE 0x0F 0x93, RM8 :SETNC SETNB; OPCODE SETE 0x0F 0x94, RM8 :SETZ; OPCODE SETNE 0x0F 0x95, RM8 :SETNZ; OPCODE SETBE 0x0F 0x96, RM8 :SETNA; OPCODE SETA 0x0F 0x97, RM8 :SETNBE; OPCODE SETS 0x0F 0x98, RM8; OPCODE SETNS 0x0F 0x99, RM8; OPCODE SETP 0x0F 0x9A, RM8 :SETPE; OPCODE SETNP 0x0F 0x9B, RM8 :SETPO; OPCODE SETL 0x0F 0x9C, RM8 :SETNGE; OPCODE SETGE 0x0F 0x9D, RM8 :SETNL; OPCODE SETLE 0x0F 0x9E, RM8 :SETNG; OPCODE SETG 0x0F 0x9F, RM8 :SETNLE; OPCODE SHLD 0x0F 0xA5,/R 16 RM16 R16 0x0F 0xA5,/R 32 RM32 R32 0x0F 0xA5,/R 32 RM64 R64; OPCODE SHRD 0x0F 0xAD,/R 16 RM16 R16 0x0F 0xAD,/R 32 RM32 R32 0x0F 0xAD,/R 32 RM64 R64; OPCODE STC 0xF9; OPCODE STD 0xFD; OPCODE STI 0xFB; OPCODE STOSB 0xAA; OPCODE STOSW 0xAB, 16; OPCODE STOSD 0xAB, 32; OPCODE STOSQ 0xAB, 32=; OPCODE STR 0x0F 0x00,/1 16 RM16 0x0F 0x00,/1 32 RM32 0x0F 0x00,/1 32 RM64; OPCODE VERR 0x0F 0x00,/4 16 RM16 0x0F 0x00,/4 32 RM32 0x0F 0x00,/4 32 RM64; OPCODE VERW 0x0F 0x00,/5 16 RM16 0x0F 0x00,/5 32 RM32 0x0F 0x00,/5 32 RM64; OPCODE WAIT 0x9B; OPCODE FWAIT 0x9B; OPCODE XADD 0x0F 0xC0,/R RM8 R8 0x0F 0xC1,/R 16 RM16 R16 0x0F 0xC1,/R 32 RM32 R32 0x0F 0xC1,/R 32 RM64 R64; OPCODE XLATB 0xD7; OPCODE ROL 0xD2,/0 RM8 CL 0xD3,/0 16 RM16 CL 0xD3,/0 32 RM32 CL 0xD3,/0 32 RM64 CL 0xC0,/0 IB &RM8 UIMM8 0xC0,/0 IB RM8 IMM8 0xC1,/0 16 IB &RM16 UIMM8 0xC1,/0 16 IB RM16 IMM8 0xC1,/0 32 IB &RM32 UIMM8 0xC1,/0 32 IB RM32 IMM8 0xC1,/0 32 IB &RM64 UIMM8 0xC1,/0 32 IB RM64 IMM8; OPCODE ROL1 0xD0,/0 RM8 0xD1,/0 16 RM16 0xD1,/0 32 RM32 0xD1,/0 32 RM64; OPCODE ROR 0xD2,/1 RM8 CL 0xD3,/1 16 RM16 CL 0xD3,/1 32 RM32 CL 0xD3,/1 32 RM64 CL 0xC0,/1 IB &RM8 UIMM8 0xC0,/1 IB RM8 IMM8 0xC1,/1 16 IB &RM16 UIMM8 0xC1,/1 16 IB RM16 IMM8 0xC1,/1 32 IB &RM32 UIMM8 0xC1,/1 32 IB RM32 IMM8 0xC1,/1 32 IB &RM64 UIMM8 0xC1,/1 32 IB RM64 IMM8; OPCODE ROR1 0xD0,/1 RM8 0xD1,/1 16 RM16 0xD1,/1 32 RM32 0xD1,/1 32 RM64; OPCODE RCL 0xD2,/2 RM8 CL 0xD3,/2 16 RM16 CL 0xD3,/2 32 RM32 CL 0xD3,/2 32 RM64 CL 0xC0,/2 IB &RM8 UIMM8 0xC0,/2 IB RM8 IMM8 0xC1,/2 16 IB &RM16 UIMM8 0xC1,/2 16 IB RM16 IMM8 0xC1,/2 32 IB &RM32 UIMM8 0xC1,/2 32 IB RM32 IMM8 0xC1,/2 32 IB &RM64 UIMM8 0xC1,/2 32 IB RM64 IMM8; OPCODE RCL1 0xD0,/2 RM8 0xD1,/2 16 RM16 0xD1,/2 32 RM32 0xD1,/2 32 RM64; OPCODE RCR 0xD2,/3 RM8 CL 0xD3,/3 16 RM16 CL 0xD3,/3 32 RM32 CL 0xD3,/3 32 RM64 CL 0xC0,/3 IB &RM8 UIMM8 0xC0,/3 IB RM8 IMM8 0xC1,/3 16 IB &RM16 UIMM8 0xC1,/3 16 IB RM16 IMM8 0xC1,/3 32 IB &RM32 UIMM8 0xC1,/3 32 IB RM32 IMM8 0xC1,/3 32 IB &RM64 UIMM8 0xC1,/3 32 IB RM64 IMM8; OPCODE RCR1 0xD0,/3 RM8 0xD1,/3 16 RM16 0xD1,/3 32 RM32 0xD1,/3 32 RM64; OPCODE SHL 0xD2,/4 RM8 CL 0xD3,/4 16 RM16 CL 0xD3,/4 32 RM32 CL 0xD3,/4 32 RM64 CL 0xC0,/4 IB &RM8 UIMM8 0xC0,/4 IB RM8 IMM8 0xC1,/4 16 IB &RM16 UIMM8 0xC1,/4 16 IB RM16 IMM8 0xC1,/4 32 IB &RM32 UIMM8 0xC1,/4 32 IB RM32 IMM8 0xC1,/4 32 IB &RM64 UIMM8 0xC1,/4 32 IB RM64 IMM8 :SAL; OPCODE SHL1 0xD0,/4 RM8 0xD1,/4 16 RM16 0xD1,/4 32 RM32 0xD1,/4 32 RM64 :SAL1; OPCODE SHR 0xD2,/5 RM8 CL 0xD3,/5 16 RM16 CL 0xD3,/5 32 RM32 CL 0xD3,/5 32 RM64 CL 0xC0,/5 IB &RM8 UIMM8 0xC0,/5 IB RM8 IMM8 0xC1,/5 16 IB &RM16 UIMM8 0xC1,/5 16 IB RM16 IMM8 0xC1,/5 32 IB &RM32 UIMM8 0xC1,/5 32 IB RM32 IMM8 0xC1,/5 32 IB &RM64 UIMM8 0xC1,/5 32 IB RM64 IMM8; OPCODE SHR1 0xD0,/5 RM8 0xD1,/5 16 RM16 0xD1,/5 32 RM32 0xD1,/5 32 RM64; OPCODE SAR 0xD2,/7 RM8 CL 0xD3,/7 16 RM16 CL 0xD3,/7 32 RM32 CL 0xD3,/7 32 RM64 CL 0xC0,/7 IB &RM8 UIMM8 0xC0,/7 IB RM8 IMM8 0xC1,/7 16 IB &RM16 UIMM8 0xC1,/7 16 IB RM16 IMM8 0xC1,/7 32 IB &RM32 UIMM8 0xC1,/7 32 IB RM32 IMM8 0xC1,/7 32 IB &RM64 UIMM8 0xC1,/7 32 IB RM64 IMM8; OPCODE SAR1 0xD0,/7 RM8 0xD1,/7 16 RM16 0xD1,/7 32 RM32 0xD1,/7 32 RM64; OPCODE FILD 0xDF,/0 M16 //Load I16 0xDB,/0 M32 //Load I32 0xDF,/5 `M64; //Load I64 OPCODE FISTP 0xDF,/7 `M64; //Store I64 OPCODE FISTTP 0xDD,/1 `M64; //Store I64 OPCODE FLD 0xD9,/0 M32 //Load F32 0xDD,/0 `M64 //Load F64 0xD9 0xC0,+I* STI; OPCODE FSTP 0xD9,/3 M32 //Store F32 0xDD,/3 `M64 //Store F64 0xDD 0xD8,+I* STI; OPCODE FST 0xD9,/2 M32 //Store F32 0xDD,/2 `M64 //Store F64 0xDD 0xD0,+I* STI; OPCODE FRSTOR 0xDD,/4 M32 0xDD,/4 M64; OPCODE FSAVE 0xDD,/6 M32 0xDD,/6 M64; OPCODE FYL2X 0xD9 0xF1,*; OPCODE FYL2XP1 0xD9 0xF9,*; OPCODE F2XM1 0xD9 0xF0,*; OPCODE FABS 0xD9 0xE1,*; OPCODE FCHS 0xD9 0xE0,*; OPCODE FSIN 0xD9 0xFE,*; OPCODE FCOS 0xD9 0xFF,*; OPCODE FPTAN 0xD9 0xF2,*; OPCODE FPATAN 0xD9 0xF3,*; OPCODE FSQRT 0xD9 0xFA,*; OPCODE FMULP 0xDE 0xC8,+I* STI ST0; OPCODE FMUL 0xD8,/1 ST0 M32 0xDC,/1 `ST0 M64 0xD8 0xC8,+I* ST0 STI 0xDC 0xC8,+I* STI ST0; OPCODE FIMUL 0xDA,/1 ST0 M32 0xDE,/1 ST0 M16; OPCODE FDIVP 0xDE 0xF8,+I* STI ST0; OPCODE FDIV 0xD8,/6 ST0 M32 0xDC,/6 `ST0 M64 0xD8 0xF0,+I* ST0 STI 0xDC 0xF8,+I* STI ST0; OPCODE FDIVRP 0xDE 0xF0,+I* STI ST0; OPCODE FDIVR 0xD8,/7 ST0 M32 0xDC,/7 `ST0 M64 0xD8 0xF8,+I* ST0 STI 0xDC 0xF0,+I* STI ST0; OPCODE FPREM 0xD9 0xF8,*; OPCODE FADDP 0xDE 0xC0,+I* STI ST0; OPCODE FADD 0xD8,/0 ST0 M32 0xDC,/0 `ST0 M64 0xD8 0xC0,+I* ST0 STI 0xDC 0xC0,+I* STI ST0; OPCODE FSUBP 0xDE 0xE8,+I* STI ST0; OPCODE FSUB 0xD8,/4 ST0 M32 0xDC,/4 `ST0 M64 0xD8 0xE0,+I* ST0 STI 0xDC 0xE8,+I* STI ST0; OPCODE FSUBRP 0xDE 0xE0,+I* STI ST0; OPCODE FSUBR 0xD8,/5 ST0 M32 0xDC,/5 `ST0 M64 0xD8 0xE8,+I* ST0 STI 0xDC 0xE0,+I* STI ST0; OPCODE FCOMIP 0xDF 0xF0,+I* ST0 STI; OPCODE FCOMI 0xDB 0xF0,+I* ST0 STI; OPCODE FCLEX 0x9B 0xDB 0xE2,*; OPCODE FNCLEX 0xDB 0xE2,*; OPCODE FSTSW 0xDF 0xE0,*; OPCODE FDECSTP 0xD9 0xF6,*; OPCODE FINCSTP 0xD9 0xF7,*; OPCODE FFREE 0xDD 0xC0,+I* STI; OPCODE FRNDINT 0xD9 0xFC,*; OPCODE FSCALE 0xD9 0xFD,*; OPCODE FXTRACT 0xD9 0xF4,*; OPCODE FLD1 0xD9 0xE8,*; OPCODE FLDL2T 0xD9 0xE9,*; OPCODE FLDL2E 0xD9 0xEA,*; OPCODE FLDPI 0xD9 0xEB,*; OPCODE FLDLG2 0xD9 0xEC,*; OPCODE FLDLN2 0xD9 0xED,*; OPCODE FLDZ 0xD9 0xEE,*; OPCODE FXCH 0xD9 0xC8,+I* STI; OPCODE FTST 0xD9 0xE4,*; OPCODE FXAM 0xD9 0xE5,*; OPCODE FINIT 0x9B 0xDB 0xE3; OPCODE FNINIT 0xDB 0xE3; OPCODE FSTCW 0xD9,/7 M16; OPCODE FLDCW 0xD9,/5 M16; OPCODE FXSAVE //512 byte 0x0F 0xAE,/0 32 M32 0x0F 0xAE,/0 32 M64; OPCODE FXRSTOR //512 byte 0x0F 0xAE,/1 32 M32 0x0F 0xAE,/1 32 M64; OPCODE WBINVD 0x0F 0x09; OPCODE CLFLUSH 0x0F 0xAE,/7 RM8; OPCODE INVLPG 0x0F 0x01,/7 RM8; OPCODE CPUID 0x0F 0xA2, 32=; OPCODE WRMSR 0x0F 0x30, 32=; OPCODE RDTSC 0x0F 0x31; OPCODE RDMSR 0x0F 0x32, 32=; OPCODE PAUSE 0xF3 0x90; OPCODE MOV_CR0_EAX 0x0F 0x22 0xC0; OPCODE MOV_EAX_CR0 0x0F 0x20 0xC0; OPCODE MOV_CR2_EAX 0x0F 0x22 0xD0; OPCODE MOV_EAX_CR2 0x0F 0x20 0xD0; OPCODE MOV_CR3_EAX 0x0F 0x22 0xD8; OPCODE MOV_EAX_CR3 0x0F 0x20 0xD8; OPCODE MOV_CR4_EAX 0x0F 0x22 0xE0; OPCODE MOV_EAX_CR4 0x0F 0x20 0xE0; OPCODE MOV_CR0_RAX 0x0F 0x22 0xC0, 32=; OPCODE MOV_RAX_CR0 0x0F 0x20 0xC0, 32=; OPCODE MOV_CR2_RAX 0x0F 0x22 0xD0, 32=; OPCODE MOV_RAX_CR2 0x0F 0x20 0xD0, 32=; OPCODE MOV_CR3_RAX 0x0F 0x22 0xD8, 32=; OPCODE MOV_RAX_CR3 0x0F 0x20 0xD8, 32=; OPCODE MOV_CR4_RAX 0x0F 0x22 0xE0, 32=; OPCODE MOV_RAX_CR4 0x0F 0x20 0xE0, 32=; OPCODE MULPD 0x66 0x0F 0x59,/R XMM XMM;