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2 commits

Author SHA1 Message Date
TomAwezome
f000c2fbdb Implement 3 operand support in assembler. 
Add support for opcodes up to 8 bytes long.
Fix 0x66 prefixed opcode instruction unassembly, at the cost of losing higher-register access on prefixed instructions.
Add almost every SSE instruction.
 2021-10-18 01:52:41 -04:00
TomAwezome
dc581ddad2 Add SSE opcodes MOVQ, PMOVMSKB, MINPS, MAXPS, XORPS, CVTSI2SD, and CVTSD2SI to OpCodes.DD. 
Add some comments in OptPass789A.CC.
 2021-10-09 05:00:13 -04:00
Renamed from ZealOS-2021-10-08-01_54_31.iso (Browse further)