Change AC97 Pci.ZC var style convention to Zeal standard.

This commit is contained in:
TomAwezome 2022-12-24 16:26:41 -05:00
parent bff3a763ea
commit ac7598808d

View file

@ -1,8 +1,10 @@
#define PCI_INTH_MAX 16 #define PCI_INTH_MAX 16
U64 @pci_int_handler[PCI_INTH_MAX]; U64 pci_int_handlers[PCI_INTH_MAX];
class @pci_info { class CPCIInfo
{
U16 vendor_id; U16 vendor_id;
U16 device_id; U16 device_id;
U16 command; U16 command;
@ -12,7 +14,8 @@ class @pci_info {
U32 cap_pointer; U32 cap_pointer;
}; };
class @pci_cap { class CPCICapability
{
U8 cap_vndr; /*Generic PCI field: PCI_CAP_ID_VNDR */ U8 cap_vndr; /*Generic PCI field: PCI_CAP_ID_VNDR */
U8 cap_next; /*Generic PCI field: next ptr. */ U8 cap_next; /*Generic PCI field: next ptr. */
U8 cap_len; /*Generic PCI field: capability length */ U8 cap_len; /*Generic PCI field: capability length */
@ -23,7 +26,8 @@ class @pci_cap {
U32 length; /*Length of the structure, in bytes. */ U32 length; /*Length of the structure, in bytes. */
}; };
U0 @get_pci_info(I64 i, @pci_info *pci) { U0 PCIInfoGet(I64 i, CPCIInfo *pci)
{
I64 j; I64 j;
pci->vendor_id = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], 0x0) &0xFFFF; pci->vendor_id = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], 0x0) &0xFFFF;
pci->device_id = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], 0x0) >> 16; pci->device_id = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], 0x0) >> 16;
@ -34,7 +38,8 @@ U0 @get_pci_info(I64 i, @pci_info *pci) {
pci->bar[j] = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], 0x10 + (0x04 * j)); pci->bar[j] = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], 0x10 + (0x04 * j));
} }
U0 @get_pci_cap(I64 i, @pci_cap *cap, I64 idx) { U0 PCIGetCapability(I64 i, CPCICapability *cap, I64 idx)
{
I64 base = 0x40 + (idx * 16); I64 base = 0x40 + (idx * 16);
U32 u32; U32 u32;
u32 = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], base); u32 = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], base);
@ -48,12 +53,14 @@ U0 @get_pci_cap(I64 i, @pci_cap *cap, I64 idx) {
cap->length = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], base + 0x0c); cap->length = PCIReadU32(i.u8[2], i.u8[1], i.u8[0], base + 0x0c);
} }
U0 @pci_reroute_interrupts(I64 base, I64 cpu) { U0 PCIInterruptReroute(I64 base, I64 cpu)
{
I64 i; I64 i;
U8 *da = dev.uncached_alias + IOAPIC_REG; U8 *da = dev.uncached_alias + IOAPIC_REG;
U32 *_d = dev.uncached_alias + IOAPIC_DATA; U32 *_d = dev.uncached_alias + IOAPIC_DATA;
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++)
{
*da = IOREDTAB + i * 2 + 1; *da = IOREDTAB + i * 2 + 1;
*_d = dev.mp_apic_ids[cpu] << 24; *_d = dev.mp_apic_ids[cpu] << 24;
*da = IOREDTAB + i * 2; *da = IOREDTAB + i * 2;
@ -61,29 +68,31 @@ U0 @pci_reroute_interrupts(I64 base, I64 cpu) {
} }
} }
I64 @pci_register_int_handler(U64 handler) { I64 PCIInterruptHandlerRegister(U64 handler)
{
if (!handler) if (!handler)
return -1; return -1;
I64 i = 0; I64 i = 0;
while (@pci_int_handler[i]) while (pci_int_handlers[i])
i++; i++;
if (i > PCI_INTH_MAX - 1) if (i > PCI_INTH_MAX - 1)
return -1; return -1;
@pci_int_handler[i] = handler; pci_int_handlers[i] = handler;
return 0; return 0;
} }
interrupt U0 @pci_interrupt_handler() { interrupt U0 PCIInterruptHandler()
{
I64 i; I64 i;
for (i = 0; i < PCI_INTH_MAX; i++) for (i = 0; i < PCI_INTH_MAX; i++)
if (@pci_int_handler[i]) if (pci_int_handlers[i])
Call(@pci_int_handler[i]); Call(pci_int_handlers[i]);
*(dev.uncached_alias + LAPIC_EOI)(U32 *) = 0; *(dev.uncached_alias + LAPIC_EOI)(U32 *) = 0;
} }
MemSet(&@pci_int_handler, NULL, sizeof(U64) * PCI_INTH_MAX); MemSet(&pci_int_handlers, NULL, sizeof(U64) * PCI_INTH_MAX);
// IntEntrySet(0x40, &@pci_interrupt_handler, IDTET_IRQ); // IntEntrySet(0x40, &PCIInterruptHandler, IDTET_IRQ);
// IntEntrySet(0x41, &@pci_interrupt_handler, IDTET_IRQ); // IntEntrySet(0x41, &PCIInterruptHandler, IDTET_IRQ);
// IntEntrySet(0x42, &@pci_interrupt_handler, IDTET_IRQ); // IntEntrySet(0x42, &PCIInterruptHandler, IDTET_IRQ);
// IntEntrySet(0x43, &@pci_interrupt_handler, IDTET_IRQ); // IntEntrySet(0x43, &PCIInterruptHandler, IDTET_IRQ);
//@pci_reroute_interrupts(0x40, 0); //PCIInterruptReroute(0x40, 0);