mirror of
https://github.com/Zeal-Operating-System/ZealOS.git
synced 2025-01-13 16:16:31 +00:00
Implement PCIBt, PCIBtr, PCIBts; use in PCI drivers.
This commit is contained in:
TomAwezome
parent
f362d5a97c
commit
a92ca05746
6 changed files with 158 additions and 161 deletions
|
|
@ -239,7 +239,7 @@ U16 E1000EEPROMRead(U8 word)
|
|||
E1000MMIOWrite(E1000_REG_EERD, 1 | word << 8);
|
||||
|
||||
temp = E1000MMIORead(E1000_REG_EERD);
|
||||
while (!Bt(&temp, E1000_EERDf_DONE))
|
||||
while (!PCIBt(&temp, E1000_EERDf_DONE))
|
||||
{
|
||||
Sleep(1);
|
||||
temp = E1000MMIORead(E1000_REG_EERD);
|
||||
|
|
@ -278,7 +278,7 @@ I64 E1000PacketReceive(U8 **packet_buffer_out, U16 *packet_length_out)
|
|||
drop = TRUE;
|
||||
}
|
||||
|
||||
if (Bt(&entry->status, E1000_RDESC_STATUSf_EOP))
|
||||
if (PCIBt(&entry->status, E1000_RDESC_STATUSf_EOP))
|
||||
{
|
||||
NetErr("E1000 PACKET RECEIVE: No EOP Set");
|
||||
drop = TRUE;
|
||||
|
|
@ -316,7 +316,7 @@ U0 E1000ReceivePacketRelease(I64 de_index)
|
|||
|
||||
Bool E1000DriverOwnsRX(CE1000DescriptorEntryRX *entry)
|
||||
{
|
||||
return Bt(&entry->status, 0); // ?? TODO #define
|
||||
return PCIBt(&entry->status, 0); // ?? TODO #define
|
||||
}
|
||||
|
||||
I64 E1000TransmitPacketAllocate(U8 **packet_buffer_out, I64 length)
|
||||
|
|
@ -330,9 +330,9 @@ I64 E1000TransmitPacketAllocate(U8 **packet_buffer_out, I64 length)
|
|||
|
||||
entry->address = *packet_buffer_out;
|
||||
entry->length = length;
|
||||
Bts(&entry->cmd, E1000_TDESC_CMDf_EOP);
|
||||
Bts(&entry->cmd, E1000_TDESC_CMDf_IFCS);
|
||||
Bts(&entry->cmd, E1000_TDESC_CMDf_RS);
|
||||
PCIBts(&entry->cmd, E1000_TDESC_CMDf_EOP);
|
||||
PCIBts(&entry->cmd, E1000_TDESC_CMDf_IFCS);
|
||||
PCIBts(&entry->cmd, E1000_TDESC_CMDf_RS);
|
||||
|
||||
NetLog("E1000 ALLOCATE TX PACKET: de_index: %X.", de_index);
|
||||
return de_index;
|
||||
|
|
@ -370,23 +370,23 @@ interrupt U0 E1000IRQ()
|
|||
|
||||
icr &= ~(E1000_ICRF_TXDW | E1000_ICRF_TXQE);
|
||||
|
||||
if (Bt(&icr, E1000_ICRf_LSC)) // 'link status change' ?
|
||||
if (PCIBt(&icr, E1000_ICRf_LSC)) // 'link status change' ?
|
||||
{
|
||||
Btr(&icr, E1000_ICRf_LSC);
|
||||
PCIBtr(&icr, E1000_ICRf_LSC);
|
||||
E1000MMIOWrite(E1000_REG_CTRL, E1000MMIORead(E1000_REG_CTRL) | E1000_CTRLF_SLU);
|
||||
}
|
||||
|
||||
if (Bt(&icr, E1000_ICRf_RXO) || Bt(&icr, E1000_ICRf_RXDMT)) // 'rx underrun / min threshold' ?
|
||||
if (PCIBt(&icr, E1000_ICRf_RXO) || PCIBt(&icr, E1000_ICRf_RXDMT)) // 'rx underrun / min threshold' ?
|
||||
{
|
||||
Btr(&icr, E1000_ICRf_RXO);
|
||||
Btr(&icr, E1000_ICRf_RXDMT);
|
||||
PCIBtr(&icr, E1000_ICRf_RXO);
|
||||
PCIBtr(&icr, E1000_ICRf_RXDMT);
|
||||
|
||||
poll = TRUE;
|
||||
}
|
||||
|
||||
if (Bt(&icr, E1000_ICRf_RXT)) // 'packet pending' ?
|
||||
if (PCIBt(&icr, E1000_ICRf_RXT)) // 'packet pending' ?
|
||||
{
|
||||
Btr(&icr, E1000_ICRf_RXT);
|
||||
PCIBtr(&icr, E1000_ICRf_RXT);
|
||||
|
||||
poll = TRUE;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -199,7 +199,7 @@ U0 PCNetSWStyleSet()
|
|||
|
||||
csr &= ~0xFF; // clears first 8 bits: SWSTYLE 8-bit register.
|
||||
csr |= PCNET_SWSTYLE_SELECTION; // set SWSTYLE to PCNet-PCI mode.
|
||||
Bts(&csr, PCNET_SWSTYLE_SSIZE32); // set SSIZE32 bit 1
|
||||
PCIBts(&csr, PCNET_SWSTYLE_SSIZE32); // set SSIZE32 bit 1
|
||||
|
||||
PCNetCSRWrite(PCNET_CSR_SOFTWARESTYLE, csr);
|
||||
}
|
||||
|
|
@ -239,7 +239,7 @@ U0 PCNetDescriptorEntryInit(CPCNetDescriptorEntry *entry, U32 buffer_address, I6
|
|||
|
||||
//if this is a Receive DE, give ownership to the card so the PCNet can fill them.
|
||||
if (is_rx)
|
||||
Bts(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
PCIBts(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
}
|
||||
|
||||
U0 PCNetBuffersAllocate()
|
||||
|
|
@ -397,11 +397,11 @@ U0 PCNetInterruptCSRSet()
|
|||
|
||||
U32 csr = PCNetCSRRead(PCNET_CSR_INTERRUPTS);
|
||||
|
||||
Btr(&csr, PCNET_INT_BSWP);
|
||||
Btr(&csr, PCNET_INT_RINTM);
|
||||
PCIBtr(&csr, PCNET_INT_BSWP);
|
||||
PCIBtr(&csr, PCNET_INT_RINTM);
|
||||
|
||||
Bts(&csr, PCNET_INT_IDONM);
|
||||
Bts(&csr, PCNET_INT_TINTM);
|
||||
PCIBts(&csr, PCNET_INT_IDONM);
|
||||
PCIBts(&csr, PCNET_INT_TINTM);
|
||||
|
||||
PCNetCSRWrite(PCNET_CSR_INTERRUPTS, csr);
|
||||
}
|
||||
|
|
@ -414,7 +414,7 @@ U0 PCNetTXAutoPadEnable()
|
|||
|
||||
U32 csr = PCNetCSRRead(PCNET_CSR_FEATURECTRL);
|
||||
|
||||
Bts(&csr, PCNET_FEATURE_APADXMT);
|
||||
PCIBts(&csr, PCNET_FEATURE_APADXMT);
|
||||
|
||||
PCNetCSRWrite(PCNET_CSR_FEATURECTRL, csr);
|
||||
}
|
||||
|
|
@ -429,10 +429,10 @@ U0 PCNetConfigModeExit()
|
|||
|
||||
U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
|
||||
|
||||
Btr(&csr, PCNET_CTRL_INIT);
|
||||
Btr(&csr, PCNET_CTRL_STOP);
|
||||
PCIBtr(&csr, PCNET_CTRL_INIT);
|
||||
PCIBtr(&csr, PCNET_CTRL_STOP);
|
||||
|
||||
Bts(&csr, PCNET_CTRL_STRT);
|
||||
PCIBts(&csr, PCNET_CTRL_STRT);
|
||||
|
||||
PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
|
||||
}
|
||||
|
|
@ -442,7 +442,7 @@ I64 PCNetDriverOwns(CPCNetDescriptorEntry* entry)
|
|||
Descriptor Entry is zero. If 0, driver owns,
|
||||
if 1, PCNet card owns it. */
|
||||
|
||||
return !Bt(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
return !PCIBt(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
}
|
||||
|
||||
I64 PCNetTransmitPacketAllocate(U8 **packet_buffer_out, I64 length)
|
||||
|
|
@ -474,9 +474,9 @@ I64 PCNetTransmitPacketAllocate(U8 **packet_buffer_out, I64 length)
|
|||
NetLog("PCNET ALLOCATE TX PACKET: Driver owns TX DE at index %d.", de_index);
|
||||
}
|
||||
|
||||
Bts(&entry->status1, PCNET_DESCRIPTORf_STP);
|
||||
PCIBts(&entry->status1, PCNET_DESCRIPTORf_STP);
|
||||
|
||||
Bts(&entry->status1, PCNET_DESCRIPTORf_ENP);
|
||||
PCIBts(&entry->status1, PCNET_DESCRIPTORf_ENP);
|
||||
|
||||
/* AMD PCNet datasheet p.1-991.
|
||||
BCNT is the usable buffer length, expressed as first
|
||||
|
|
@ -507,9 +507,9 @@ U0 PCNetTransmitPacketFinish(I64 de_index)
|
|||
|
||||
CPCNetDescriptorEntry *entry = &pcnet.tx_de_buffer[de_index * sizeof(CPCNetDescriptorEntry)];
|
||||
|
||||
Bts(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
PCIBts(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
NetLog("PCNET FINISH TX PACKET: TX DE index: %X, OWN bit of entry at entry: %b.",
|
||||
de_index, Bt(&entry->status1, PCNET_DESCRIPTORf_OWN));
|
||||
de_index, PCIBt(&entry->status1, PCNET_DESCRIPTORf_OWN));
|
||||
}
|
||||
|
||||
U0 EthernetFrameFinish(I64 de_index)
|
||||
|
|
@ -553,7 +553,7 @@ U0 PCNetReceivePacketRelease(I64 de_index)
|
|||
|
||||
CPCNetDescriptorEntry *entry = &pcnet.rx_de_buffer[de_index * sizeof(CPCNetDescriptorEntry)];
|
||||
|
||||
Bts(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
PCIBts(&entry->status1, PCNET_DESCRIPTORf_OWN);
|
||||
}
|
||||
|
||||
interrupt U0 PCNetIRQ()
|
||||
|
|
@ -586,7 +586,7 @@ interrupt U0 PCNetIRQ()
|
|||
PCNetReceivePacketRelease(de_index);
|
||||
}
|
||||
|
||||
Bts(&csr, PCNET_CTRL_RINT);
|
||||
PCIBts(&csr, PCNET_CTRL_RINT);
|
||||
|
||||
PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
|
||||
|
||||
|
|
@ -649,10 +649,10 @@ U0 PCNetInit()
|
|||
PCNet32BitModeEnable;
|
||||
|
||||
U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
|
||||
NetLog("PCNET INIT START: what is INIT ?: %d", Bt(&csr, PCNET_CTRL_INIT));
|
||||
NetLog("PCNET INIT START: what is STRT ?: %d", Bt(&csr, PCNET_CTRL_STRT));
|
||||
NetLog("PCNET INIT START: what is STOP ?: %d", Bt(&csr, PCNET_CTRL_STOP));
|
||||
NetLog("PCNET INIT START: what is RINT ?: %d", Bt(&csr, PCNET_CTRL_RINT));
|
||||
NetLog("PCNET INIT START: what is INIT ?: %d", PCIBt(&csr, PCNET_CTRL_INIT));
|
||||
NetLog("PCNET INIT START: what is STRT ?: %d", PCIBt(&csr, PCNET_CTRL_STRT));
|
||||
NetLog("PCNET INIT START: what is STOP ?: %d", PCIBt(&csr, PCNET_CTRL_STOP));
|
||||
NetLog("PCNET INIT START: what is RINT ?: %d", PCIBt(&csr, PCNET_CTRL_RINT));
|
||||
|
||||
|
||||
PCNetSWStyleSet;
|
||||
|
|
@ -672,10 +672,10 @@ U0 PCNetInit()
|
|||
PCNetCSRWrite(0, PCNetCSRRead(0) | 1 | 1 << 6); // ?
|
||||
|
||||
csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
|
||||
NetLog("PCNET INIT UPLOAD: what is INIT ?: %d", Bt(&csr, PCNET_CTRL_INIT));
|
||||
NetLog("PCNET INIT UPLOAD: what is STRT ?: %d", Bt(&csr, PCNET_CTRL_STRT));
|
||||
NetLog("PCNET INIT UPLOAD: what is STOP ?: %d", Bt(&csr, PCNET_CTRL_STOP));
|
||||
NetLog("PCNET INIT UPLOAD: what is RINT ?: %d", Bt(&csr, PCNET_CTRL_RINT));
|
||||
NetLog("PCNET INIT UPLOAD: what is INIT ?: %d", PCIBt(&csr, PCNET_CTRL_INIT));
|
||||
NetLog("PCNET INIT UPLOAD: what is STRT ?: %d", PCIBt(&csr, PCNET_CTRL_STRT));
|
||||
NetLog("PCNET INIT UPLOAD: what is STOP ?: %d", PCIBt(&csr, PCNET_CTRL_STOP));
|
||||
NetLog("PCNET INIT UPLOAD: what is RINT ?: %d", PCIBt(&csr, PCNET_CTRL_RINT));
|
||||
|
||||
while (!(PCNetCSRRead(0) & 1 << 8)) // ?
|
||||
Yield;
|
||||
|
|
@ -685,15 +685,15 @@ U0 PCNetInit()
|
|||
Sleep(100); //? necessary?
|
||||
|
||||
csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
|
||||
NetLog("PCNET INIT END: what is INIT ?: %d", Bt(&csr, PCNET_CTRL_INIT));
|
||||
NetLog("PCNET INIT END: what is STRT ?: %d", Bt(&csr, PCNET_CTRL_STRT));
|
||||
NetLog("PCNET INIT END: what is STOP ?: %d", Bt(&csr, PCNET_CTRL_STOP));
|
||||
NetLog("PCNET INIT END: what is RINT ?: %d", Bt(&csr, PCNET_CTRL_RINT));
|
||||
NetLog("PCNET INIT END: what is TXON ?: %d", Bt(&csr, 4));
|
||||
NetLog("PCNET INIT END: what is RXON ?: %d", Bt(&csr, 5));
|
||||
NetLog("PCNET INIT END: what is INIT ?: %d", PCIBt(&csr, PCNET_CTRL_INIT));
|
||||
NetLog("PCNET INIT END: what is STRT ?: %d", PCIBt(&csr, PCNET_CTRL_STRT));
|
||||
NetLog("PCNET INIT END: what is STOP ?: %d", PCIBt(&csr, PCNET_CTRL_STOP));
|
||||
NetLog("PCNET INIT END: what is RINT ?: %d", PCIBt(&csr, PCNET_CTRL_RINT));
|
||||
NetLog("PCNET INIT END: what is TXON ?: %d", PCIBt(&csr, 4));
|
||||
NetLog("PCNET INIT END: what is RXON ?: %d", PCIBt(&csr, 5));
|
||||
|
||||
csr = PCNetCSRRead(PCNET_CSR_POLLINT);
|
||||
NetLog("PCNET INIT END: what is POLLINT ?: %d", Bt(&csr, PCNET_CTRL_RINT));
|
||||
NetLog("PCNET INIT END: what is POLLINT ?: %d", PCIBt(&csr, PCNET_CTRL_RINT));
|
||||
|
||||
NetLog("PCNET INIT END: Redirecting interrupts.");
|
||||
PCNetInterruptsSetup;
|
||||
|
|
@ -751,7 +751,7 @@ U0 NetStop()
|
|||
{ // Halt network activity by setting STOP bit on Status CSR.
|
||||
U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
|
||||
|
||||
Bts(&csr, PCNET_CTRL_STOP);
|
||||
PCIBts(&csr, PCNET_CTRL_STOP);
|
||||
|
||||
PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
|
||||
|
||||
|
|
@ -761,7 +761,7 @@ U0 NetStart()
|
|||
{ // Continue network activity. Setting START bit clears STOP/INIT.
|
||||
U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
|
||||
|
||||
Bts(&csr, PCNET_CTRL_STRT);
|
||||
PCIBts(&csr, PCNET_CTRL_STRT);
|
||||
|
||||
PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -32,24 +32,24 @@ U0 AHCIDebug(I64 port_num)
|
|||
"\nAHCI Port: %d", port_num;
|
||||
|
||||
"\nPort Interrupt Status: %b", port->interrupt_status;
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_CPDS))
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_CPDS))
|
||||
"\n\tCold Port Detect Status";
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_TFE))
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_TFE))
|
||||
"\n\tTask File Error";
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_HBFS))
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_HBFS))
|
||||
"\n\tHost Bus Fatal Error";
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_HBDS))
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_HBDS))
|
||||
"\n\tHost Bus Data Error";
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_IFS))
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_IFS))
|
||||
"\n\tSATA Interface Fatal Error";
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_INFS))
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_INFS))
|
||||
"\n\tSATA Interface Non-Fatal Error";
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_OFS))
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_OFS))
|
||||
"\n\tOverflow Status (HBA RX bytes > PRDT bytes)";
|
||||
"\nPort Command: %b", port->command;
|
||||
"\nPort Command Issue: %b", port->cmd_issue;
|
||||
"\nPort Task File Data: %b", port->task_file_data;
|
||||
if (Bt(&port->task_file_data, AHCI_PxTFDf_STS_ERR))
|
||||
if (PCIBt(&port->task_file_data, AHCI_PxTFDf_STS_ERR))
|
||||
{
|
||||
"\n\tTask File Data Error";
|
||||
"\n\tTask File Data Error Register: %b", port->task_file_data.u8[1];
|
||||
|
|
@ -58,27 +58,27 @@ U0 AHCIDebug(I64 port_num)
|
|||
"\nPort SATA Status: %b", port->sata_status;
|
||||
"\nPort SATA Ctrl: %b", port->sata_ctrl;
|
||||
"\nPort SATA Error: %b", port->sata_error;
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_ERR_I))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_ERR_I))
|
||||
"\n\tRecovered Data Integrity Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_ERR_M))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_ERR_M))
|
||||
"\n\tRecovered Communication Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_ERR_T))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_ERR_T))
|
||||
"\n\tTransient Data Integrity Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_ERR_C))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_ERR_C))
|
||||
"\n\tPersistent Communication Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_ERR_P))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_ERR_P))
|
||||
"\n\tSATA Protocol Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_ERR_E))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_ERR_E))
|
||||
"\n\tInternal Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_DIAG_I))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_DIAG_I))
|
||||
"\n\tPHY Internal Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_DIAG_C))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_DIAG_C))
|
||||
"\n\tLink Layer CRC Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_DIAG_H))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_DIAG_H))
|
||||
"\n\tHandshake Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_DIAG_S))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_DIAG_S))
|
||||
"\n\tLink Sequence Error";
|
||||
if (Bt(&port->sata_error, AHCI_PxSERR_DIAG_T))
|
||||
if (PCIBt(&port->sata_error, AHCI_PxSERR_DIAG_T))
|
||||
"\n\tTransport State Transition Error";
|
||||
"\nPort SATA Active: %b", port->sata_active;
|
||||
"\nPort SATA Notif: %b", port->sata_notif;
|
||||
|
|
@ -92,14 +92,14 @@ U0 AHCIDebug(I64 port_num)
|
|||
"\nHBA Ports Implemented: %b", hba->ports_implemented;
|
||||
"\nHBA Version: 0x%0X", hba->version;
|
||||
"\nHBA Ext Capabilities: %b", hba->caps_ext;
|
||||
if (Bt(&hba->caps_ext, AHCI_CAPSEXTf_BOH))
|
||||
if (PCIBt(&hba->caps_ext, AHCI_CAPSEXTf_BOH))
|
||||
"\n\tBIOS/OS Handoff supported.";
|
||||
if (Bt(&hba->caps_ext, AHCI_CAPSEXTf_NVMP))
|
||||
if (PCIBt(&hba->caps_ext, AHCI_CAPSEXTf_NVMP))
|
||||
"\n\tNVMHCI Supported (Non-Volatile Memory Host Controller Interface)";
|
||||
"\nHBA BIOS/OS Handoff: %b", hba->bohc;
|
||||
if (Bt(&hba->bohc, AHCI_BOHCf_BOS))
|
||||
if (PCIBt(&hba->bohc, AHCI_BOHCf_BOS))
|
||||
"\n\tBIOS owns AHCI Controller";
|
||||
if (Bt(&hba->bohc, AHCI_BOHCf_BB))
|
||||
if (PCIBt(&hba->bohc, AHCI_BOHCf_BB))
|
||||
"\n\tBIOS Busy";
|
||||
|
||||
"\n";
|
||||
|
|
@ -151,20 +151,20 @@ U0 AHCIPortCmdStop(I64 port_num)
|
|||
{//Stop command engine on port.
|
||||
CAHCIPort *port = &blkdev.ahci_hba->ports[port_num];
|
||||
|
||||
Btr(&port->command, AHCI_PxCMDf_ST);
|
||||
Btr(&port->command, AHCI_PxCMDf_FRE);
|
||||
PCIBtr(&port->command, AHCI_PxCMDf_ST);
|
||||
PCIBtr(&port->command, AHCI_PxCMDf_FRE);
|
||||
|
||||
while (Bt(&port->command, AHCI_PxCMDf_CR) || Bt(&port->command, AHCI_PxCMDf_FR));
|
||||
while (PCIBt(&port->command, AHCI_PxCMDf_CR) || PCIBt(&port->command, AHCI_PxCMDf_FR));
|
||||
}
|
||||
|
||||
U0 AHCIPortCmdStart(I64 port_num)
|
||||
{//Start command engine on port.
|
||||
CAHCIPort *port = &blkdev.ahci_hba->ports[port_num];
|
||||
|
||||
while (Bt(&port->command, AHCI_PxCMDf_CR));
|
||||
while (PCIBt(&port->command, AHCI_PxCMDf_CR));
|
||||
|
||||
Bts(&port->command, AHCI_PxCMDf_FRE);
|
||||
Bts(&port->command, AHCI_PxCMDf_ST);
|
||||
PCIBts(&port->command, AHCI_PxCMDf_FRE);
|
||||
PCIBts(&port->command, AHCI_PxCMDf_ST);
|
||||
}
|
||||
|
||||
Bool AHCIPortWait(I64 port_num, F64 timeout, Bool throwing=TRUE)
|
||||
|
|
@ -231,10 +231,10 @@ U0 AHCIPortCmdWait(I64 port_num, I64 cmd_slot)
|
|||
|
||||
while (TRUE)
|
||||
{
|
||||
if (!Bt(&port->cmd_issue, cmd_slot)) //When command has been processed
|
||||
if (!PCIBt(&port->cmd_issue, cmd_slot)) //When command has been processed
|
||||
break;
|
||||
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_TFE)) //Task File Error ($LK,"ATAS_ERR",A="MN:ATAS_ERR"$)
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_TFE)) //Task File Error ($LK,"ATAS_ERR",A="MN:ATAS_ERR"$)
|
||||
{
|
||||
error:
|
||||
if (AHCI_DEBUG)
|
||||
|
|
@ -250,7 +250,7 @@ error:
|
|||
Yield; // don't hang OS
|
||||
}
|
||||
|
||||
if (Bt(&port->interrupt_status, AHCI_PxIf_TFE)) //Second safety check
|
||||
if (PCIBt(&port->interrupt_status, AHCI_PxIf_TFE)) //Second safety check
|
||||
goto error;
|
||||
}
|
||||
|
||||
|
|
@ -271,7 +271,7 @@ I64 AHCIAtapiCapacityGet(CBlkDev *bd)
|
|||
|
||||
buf = CAlloc(8, sys_task->code_heap);
|
||||
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
|
||||
cmd_table = cmd_header->cmd_table_base;
|
||||
MemSet(cmd_table, 0, sizeof(CPortCmdTable));
|
||||
|
|
@ -284,12 +284,12 @@ I64 AHCIAtapiCapacityGet(CBlkDev *bd)
|
|||
cmd_fis = cmd_table->cmd_fis;
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
cmd_fis->command = ATA_PACKET;
|
||||
cmd_table->acmd[0] = ATAPI_READ_CAPACITY >> 8;
|
||||
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
Bts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
PCIBts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
|
||||
try
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
|
@ -316,7 +316,7 @@ Bool AHCIAtapiSync(CBlkDev *bd)
|
|||
throw('AHCI');
|
||||
}
|
||||
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
|
||||
cmd_table = cmd_header->cmd_table_base;
|
||||
MemSet(cmd_table, 0, sizeof(CPortCmdTable));
|
||||
|
|
@ -324,12 +324,12 @@ Bool AHCIAtapiSync(CBlkDev *bd)
|
|||
cmd_fis = cmd_table->cmd_fis;
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
cmd_fis->command = ATA_PACKET;
|
||||
cmd_table->acmd[0] = ATAPI_SYNC_CACHE >> 8;
|
||||
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
Bts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
PCIBts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
|
||||
try
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
|
@ -357,7 +357,7 @@ Bool AHCIAtapiClose(CBlkDev *bd, I64 close_field=0x200, I64 track=0)
|
|||
throw('AHCI');
|
||||
}
|
||||
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
|
||||
cmd_table = cmd_header->cmd_table_base;
|
||||
MemSet(cmd_table, 0, sizeof(CPortCmdTable));
|
||||
|
|
@ -365,7 +365,7 @@ Bool AHCIAtapiClose(CBlkDev *bd, I64 close_field=0x200, I64 track=0)
|
|||
cmd_fis = cmd_table->cmd_fis;
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
cmd_fis->command = ATA_PACKET;
|
||||
|
||||
MemSet(&close_cmd, 0, sizeof(CAtapiCloseCmd));
|
||||
|
|
@ -375,7 +375,7 @@ Bool AHCIAtapiClose(CBlkDev *bd, I64 close_field=0x200, I64 track=0)
|
|||
MemCopy(&cmd_table->acmd, &close_cmd, sizeof(CAtapiCloseCmd));
|
||||
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
Bts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
PCIBts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
|
||||
try
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
|
@ -402,7 +402,7 @@ Bool AHCIAtapiBlank(CBlkDev *bd, Bool minimal=TRUE)
|
|||
throw('AHCI');
|
||||
}
|
||||
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
|
||||
cmd_table = cmd_header->cmd_table_base;
|
||||
MemSet(cmd_table, 0, sizeof(CPortCmdTable));
|
||||
|
|
@ -410,13 +410,13 @@ Bool AHCIAtapiBlank(CBlkDev *bd, Bool minimal=TRUE)
|
|||
cmd_fis = cmd_table->cmd_fis;
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
cmd_fis->command = ATA_PACKET;
|
||||
cmd_table->acmd[0] = ATAPI_BLANK >> 8;
|
||||
cmd_table->acmd[1] = minimal;
|
||||
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
Bts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
PCIBts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
|
||||
try
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
|
@ -452,7 +452,7 @@ Bool AHCIAtapiModeWriteSelect(CBlkDev *bd)
|
|||
mode_list->page.block_type = 8; // Mode 1: 2048-size blocks of data
|
||||
mode_list->page.packet_size = EndianU32(16);// Number of User Data Blocks per Fixed Packet. DVD media default: 16.
|
||||
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
|
||||
cmd_table = cmd_header->cmd_table_base;
|
||||
MemSet(cmd_table, 0, sizeof(CPortCmdTable));
|
||||
|
|
@ -465,12 +465,12 @@ Bool AHCIAtapiModeWriteSelect(CBlkDev *bd)
|
|||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
cmd_fis->feature_low= 0x01; // Core Feature, 'mandatory'
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
cmd_fis->command = ATA_PACKET;
|
||||
cmd_table->acmd[0] = ATAPI_MODE_SELECT >> 8;
|
||||
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
Bts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
PCIBts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
|
||||
try
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
|
@ -497,7 +497,7 @@ Bool AHCIAtapiStartStop(CBlkDev *bd, Bool start)
|
|||
throw('AHCI');
|
||||
}
|
||||
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_A);
|
||||
|
||||
cmd_table = cmd_header->cmd_table_base;
|
||||
MemSet(cmd_table, 0, sizeof(CPortCmdTable));
|
||||
|
|
@ -505,13 +505,13 @@ Bool AHCIAtapiStartStop(CBlkDev *bd, Bool start)
|
|||
cmd_fis = cmd_table->cmd_fis;
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
cmd_fis->command = ATA_PACKET;
|
||||
cmd_table->acmd[0] = ATAPI_START_STOP_UNIT >> 8;
|
||||
cmd_table->acmd[4] = start;
|
||||
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
Bts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
PCIBts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
|
||||
try
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
|
@ -573,7 +573,7 @@ U0 AHCIPortIdentify(CBlkDev *bd)
|
|||
cmd_fis = cmd_table->cmd_fis;
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS.
|
||||
|
||||
if (port->signature == AHCI_PxSIG_ATAPI)
|
||||
cmd_fis->command = ATA_IDENTIFY_PACKET;
|
||||
|
|
@ -585,7 +585,7 @@ U0 AHCIPortIdentify(CBlkDev *bd)
|
|||
//Wait on previous command to complete.
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
|
||||
Bts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
PCIBts(&port->cmd_issue, cmd_slot); //Issue the command.
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
||||
Free(bd->dev_id_record);
|
||||
|
|
@ -615,14 +615,14 @@ U8 *AHCIBufferAlign(CBlkDev *bd, U8 *user_buf, I64 buf_size, Bool write)
|
|||
Free(bd->prd_buf);
|
||||
bd->prd_buf = MAlloc(buf_size, sys_task->code_heap);
|
||||
|
||||
Bts(&bd->flags, BDf_INTERNAL_BUF);
|
||||
PCIBts(&bd->flags, BDf_INTERNAL_BUF);
|
||||
|
||||
if (write)
|
||||
MemCopy(bd->prd_buf, user_buf, buf_size);
|
||||
|
||||
return bd->prd_buf;
|
||||
}
|
||||
Btr(&bd->flags, BDF_INTERNAL_BUF);
|
||||
PCIBtr(&bd->flags, BDF_INTERNAL_BUF);
|
||||
|
||||
return user_buf;
|
||||
}
|
||||
|
|
@ -686,7 +686,7 @@ I64 AHCIAtaBlksRW(CBlkDev *bd, U8 *buf, I64 blk, I64 count, Bool write)
|
|||
cmd_fis = cmd_table->cmd_fis;
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS
|
||||
|
||||
if (write) //Assumed support for LBA48.
|
||||
cmd_fis->command = ATA_WRITE_DMA_EXT;
|
||||
|
|
@ -706,7 +706,7 @@ I64 AHCIAtaBlksRW(CBlkDev *bd, U8 *buf, I64 blk, I64 count, Bool write)
|
|||
//Wait on previous command to complete.
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
//Issue the command.
|
||||
Bts(&port->cmd_issue, cmd_slot);
|
||||
PCIBts(&port->cmd_issue, cmd_slot);
|
||||
//Wait on command to finish.
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
||||
|
|
@ -805,7 +805,7 @@ I64 AHCIAtapiBlksRead(CBlkDev *bd, U8 *buf, I64 blk, I64 count, Bool lock=TRUE)
|
|||
|
||||
if (!internal_buf) throw('AHCI');
|
||||
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_A); //Set ATAPI flag in command header
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_A); //Set ATAPI flag in command header
|
||||
|
||||
cmd_table = cmd_header->cmd_table_base;
|
||||
MemSet(cmd_table, 0, sizeof(CPortCmdTable));
|
||||
|
|
@ -828,7 +828,7 @@ I64 AHCIAtapiBlksRead(CBlkDev *bd, U8 *buf, I64 blk, I64 count, Bool lock=TRUE)
|
|||
MemSet(cmd_fis, 0, sizeof(CFisH2D));
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS
|
||||
|
||||
cmd_fis->feature_low = 1; //Necessary?
|
||||
cmd_fis->command = ATA_PACKET;
|
||||
|
|
@ -843,7 +843,7 @@ I64 AHCIAtapiBlksRead(CBlkDev *bd, U8 *buf, I64 blk, I64 count, Bool lock=TRUE)
|
|||
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
|
||||
Bts(&port->cmd_issue, cmd_slot);
|
||||
PCIBts(&port->cmd_issue, cmd_slot);
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
||||
if (bd->flags & BDF_INTERNAL_BUF)
|
||||
|
|
@ -892,8 +892,8 @@ I64 AHCIAtapiBlksWrite(CBlkDev *bd, U8 *buf, I64 blk, I64 count, Bool lock=TRUE)
|
|||
|
||||
if (!internal_buf) throw('AHCI');
|
||||
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_A); //Set ATAPI flag in command header
|
||||
Bts(&cmd_header->desc, AHCI_CH_DESCf_W); //Set WRITE flag in command header
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_A); //Set ATAPI flag in command header
|
||||
PCIBts(&cmd_header->desc, AHCI_CH_DESCf_W); //Set WRITE flag in command header
|
||||
|
||||
cmd_table = cmd_header->cmd_table_base;
|
||||
MemSet(cmd_table, 0, sizeof(CPortCmdTable));
|
||||
|
|
@ -915,7 +915,7 @@ I64 AHCIAtapiBlksWrite(CBlkDev *bd, U8 *buf, I64 blk, I64 count, Bool lock=TRUE)
|
|||
MemSet(cmd_fis, 0, sizeof(CFisH2D));
|
||||
|
||||
cmd_fis->type = FISt_H2D;
|
||||
Bts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS
|
||||
PCIBts(&cmd_fis->desc, AHCI_CF_DESCf_C); //Set Command bit in H2D FIS
|
||||
|
||||
cmd_fis->command = ATA_PACKET;
|
||||
|
||||
|
|
@ -928,7 +928,7 @@ I64 AHCIAtapiBlksWrite(CBlkDev *bd, U8 *buf, I64 blk, I64 count, Bool lock=TRUE)
|
|||
|
||||
AHCIPortWait(bd->port_num, tS + 2);
|
||||
|
||||
Bts(&port->cmd_issue, cmd_slot);
|
||||
PCIBts(&port->cmd_issue, cmd_slot);
|
||||
AHCIPortCmdWait(bd->port_num, cmd_slot);
|
||||
|
||||
if (bd->flags & BDF_INTERNAL_BUF)
|
||||
|
|
@ -1044,9 +1044,9 @@ Bool AHCIAtaInit(CBlkDev *bd)
|
|||
|
||||
U0 AHCIHbaReset()
|
||||
{
|
||||
Bts(&blkdev.ahci_hba->ghc, AHCI_GHCf_HBA_RESET);
|
||||
while (Bt(&blkdev.ahci_hba->ghc, AHCI_GHCf_HBA_RESET));
|
||||
Bts(&blkdev.ahci_hba->ghc, AHCI_GHCf_AHCI_ENABLE);
|
||||
PCIBts(&blkdev.ahci_hba->ghc, AHCI_GHCf_HBA_RESET);
|
||||
while (PCIBt(&blkdev.ahci_hba->ghc, AHCI_GHCf_HBA_RESET));
|
||||
PCIBts(&blkdev.ahci_hba->ghc, AHCI_GHCf_AHCI_ENABLE);
|
||||
}
|
||||
|
||||
U0 AHCIInit()
|
||||
|
|
@ -1070,19 +1070,19 @@ U0 AHCIInit()
|
|||
blkdev.ahci_hba = hba;
|
||||
|
||||
|
||||
Bts(&blkdev.ahci_hba->ghc, AHCI_GHCf_AHCI_ENABLE);
|
||||
PCIBts(&blkdev.ahci_hba->ghc, AHCI_GHCf_AHCI_ENABLE);
|
||||
"AHCI: GHC.AE set\n";
|
||||
|
||||
//Transferring ownership from BIOS if supported.
|
||||
if (Bt(&hba->caps_ext, AHCI_CAPSEXTf_BOH))
|
||||
if (PCIBt(&hba->caps_ext, AHCI_CAPSEXTf_BOH))
|
||||
{
|
||||
Bts(&hba->bohc, AHCI_BOHCf_OOS);
|
||||
PCIBts(&hba->bohc, AHCI_BOHCf_OOS);
|
||||
"AHCI: Transferring ownership from BIOS\n";
|
||||
|
||||
while (Bt(&hba->bohc, AHCI_BOHCf_BOS));
|
||||
while (PCIBt(&hba->bohc, AHCI_BOHCf_BOS));
|
||||
|
||||
Sleep(25);
|
||||
if (Bt(&hba->bohc, AHCI_BOHCf_BB)) //if Bios Busy is still set after 25 mS, wait 2 seconds.
|
||||
if (PCIBt(&hba->bohc, AHCI_BOHCf_BB)) //if Bios Busy is still set after 25 mS, wait 2 seconds.
|
||||
Sleep(2000);
|
||||
}
|
||||
|
||||
|
|
@ -1091,7 +1091,7 @@ U0 AHCIInit()
|
|||
|
||||
for (i = 0; i < AHCI_MAX_PORTS; i++)
|
||||
{
|
||||
if (Bt(&hba->ports_implemented, i))
|
||||
if (PCIBt(&hba->ports_implemented, i))
|
||||
{//$BK,1$Make ports idle?$BK,0$
|
||||
port = &hba->ports[i];
|
||||
"AHCI: Port %2d signature 0x%08X ", i, port->signature;
|
||||
|
|
@ -1099,7 +1099,7 @@ U0 AHCIInit()
|
|||
{
|
||||
if (port->signature == AHCI_PxSIG_ATAPI)
|
||||
{
|
||||
Bts(&port->command, AHCI_PxCMDf_ATAPI);
|
||||
PCIBts(&port->command, AHCI_PxCMDf_ATAPI);
|
||||
"ATAPI drive\n";
|
||||
}
|
||||
else if (port->signature == AHCI_PxSIG_ATA)
|
||||
|
|
@ -1129,7 +1129,7 @@ Bool AHCIBootDVDProbeAll(CBlkDev *bd)
|
|||
|
||||
for (i = 0; i < AHCI_MAX_PORTS; i++)
|
||||
{
|
||||
if (Bt(&blkdev.ahci_hba->ports_implemented, i))
|
||||
if (PCIBt(&blkdev.ahci_hba->ports_implemented, i))
|
||||
{
|
||||
port = &blkdev.ahci_hba->ports[i];
|
||||
"AHCI: BootDVDProbeAll: Saw port at %2d with signature 0x%0X\n", i, port->signature;
|
||||
|
|
|
|||
|
|
@ -8,47 +8,10 @@ $LK,"KernelB",A="FF:::/StartOS.ZC,KernelB"$ StartOS.ZC
|
|||
#help_file "::/Doc/Bit"
|
||||
public _intern IC_BSF I64 Bsf(I64 bit_field_val); //Scan forward from lowest for 1st set. -1 if not found.
|
||||
public _intern IC_BSR I64 Bsr(I64 bit_field_val); //Scan rev from highest for 1st set. -1 if not found.
|
||||
//public _intern IC_BT Bool Bt( U8 *bit_field, I64 bit); //Bit test.
|
||||
public _intern IC_BT Bool Bt( U8 *bit_field, I64 bit); //Bit test.
|
||||
public _intern IC_BTC Bool Btc( U8 *bit_field, I64 bit); //Bit test and complement (same as xor with 1).
|
||||
//public _intern IC_BTR Bool Btr( U8 *bit_field, I64 bit); //Bit test and reset to zero.
|
||||
//public _intern IC_BTS Bool Bts( U8 *bit_field, I64 bit); //Bit test and set to one.
|
||||
|
||||
// TODO FIXME DEBUG: Fix ICBitOps bugs when using on bare metal into PCI device memory-mapped areas.
|
||||
// Temporarily manually defining functions for Bt, Btr, and Bts below.
|
||||
// (certain Bt(), Btr(), and Bts() on AHCI memory areas using variable (reg, not imm) bit param
|
||||
// caused strange crashes on a Ryzen with Gigabyte brand motherboard, all PCI devices AMD brand.
|
||||
// Bit test compiler implementation needs to be researched to fix those bugs.)
|
||||
|
||||
Bool Bt(U8 reg RBX *bit_field, I64 reg RDX bit)
|
||||
{
|
||||
bit_field += bit / 8;
|
||||
bit &= 7;
|
||||
return (*bit_field & (1 << bit)) >> bit;
|
||||
}
|
||||
|
||||
Bool Btr(U8 reg RDX *bit_field, I64 reg RBX bit)
|
||||
{
|
||||
U64 reg R9 chunk_mod = (bit & 31);
|
||||
U64 chunk_bit = 1 << chunk_mod;
|
||||
bit_field(U32 *) += bit / 32;
|
||||
Bool reg R8 result = (*(bit_field(U32 *)) & chunk_bit) >> chunk_mod;
|
||||
|
||||
*(bit_field(U32 *)) &= ~(chunk_bit);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
Bool Bts(U8 reg RDX *bit_field, I64 reg RBX bit)
|
||||
{
|
||||
U64 reg R9 chunk_mod = (bit & 31);
|
||||
U64 chunk_bit = 1 << chunk_mod;
|
||||
bit_field(U32 *) += bit / 32;
|
||||
Bool reg R8 result = (*(bit_field(U32 *)) & chunk_bit) >> chunk_mod;
|
||||
|
||||
*(bit_field(U32 *)) |= chunk_bit;
|
||||
|
||||
return result;
|
||||
}
|
||||
public _intern IC_BTR Bool Btr( U8 *bit_field, I64 bit); //Bit test and reset to zero.
|
||||
public _intern IC_BTS Bool Bts( U8 *bit_field, I64 bit); //Bit test and set to one.
|
||||
|
||||
public _intern IC_LBTC Bool LBtc( U8 *bit_field, I64 bit); //Locked bit test and complement (xor with 1).
|
||||
public _intern IC_LBTR Bool LBtr( U8 *bit_field, I64 bit); //Locked bit test and reset to zero.
|
||||
|
|
|
|||
|
|
@ -622,6 +622,9 @@ public extern U0 PCIWriteU32(I64 bus, I64 dev, I64 fun, I64 rg, I64 val);
|
|||
public extern U0 PCIWriteU8( I64 bus, I64 dev, I64 fun, I64 rg, I64 val);
|
||||
public _extern SYS_PCIBIOS_SERVICE_DIR U32 sys_PCIBIOS_service_dir;//Far call routine in the BIOS
|
||||
public _extern SYS_PCI_SERVICES U32 sys_pci_services;//Far call routine in the BIOS
|
||||
public extern Bool PCIBt( U8 *bit_field, I64 bit); // MOV-based Bt for use in PCI device memory-mapped IO areas. See $LK+PU,"Bt()",A="FF:::/Kernel/KernelB.HH,Bt("$.
|
||||
public extern Bool PCIBtr( U8 *bit_field, I64 bit); // MOV-based Btr for use in PCI device memory-mapped IO areas. See $LK+PU,"Btr()",A="FF:::/Kernel/KernelB.HH,Btr("$.
|
||||
public extern Bool PCIBts( U8 *bit_field, I64 bit); // MOV-based Bts for use in PCI device memory-mapped IO areas. See $LK+PU,"Bts()",A="FF:::/Kernel/KernelB.HH,Bts("$.
|
||||
|
||||
#help_index "Processor"
|
||||
public extern U8 *IntEntryGet(I64 irq);
|
||||
|
|
|
|||
|
|
@ -126,3 +126,34 @@ else bus, dev, fun.
|
|||
pci_end:
|
||||
return res;
|
||||
}
|
||||
|
||||
Bool PCIBt(U8 reg RBX *bit_field, I64 reg RDX bit)
|
||||
{ // MOV-based Bt for use in PCI device memory-mapped IO areas. See $LK+PU,"Bt()",A="FF:::/Kernel/KernelB.HH,Bt("$.
|
||||
bit_field += bit / 8;
|
||||
bit &= 7;
|
||||
return (*bit_field & (1 << bit)) >> bit;
|
||||
}
|
||||
|
||||
Bool PCIBtr(U8 reg RDX *bit_field, I64 reg RBX bit)
|
||||
{ // MOV-based Btr for use in PCI device memory-mapped IO areas. See $LK+PU,"Btr()",A="FF:::/Kernel/KernelB.HH,Btr("$.
|
||||
U64 reg R9 chunk_mod = (bit & 31);
|
||||
U64 chunk_bit = 1 << chunk_mod;
|
||||
bit_field(U32 *) += bit / 32;
|
||||
Bool reg R8 result = (*(bit_field(U32 *)) & chunk_bit) >> chunk_mod;
|
||||
|
||||
*(bit_field(U32 *)) &= ~(chunk_bit);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
Bool PCIBts(U8 reg RDX *bit_field, I64 reg RBX bit)
|
||||
{ // MOV-based Bts for use in PCI device memory-mapped IO areas. See $LK+PU,"Bts()",A="FF:::/Kernel/KernelB.HH,Bts("$.
|
||||
U64 reg R9 chunk_mod = (bit & 31);
|
||||
U64 chunk_bit = 1 << chunk_mod;
|
||||
bit_field(U32 *) += bit / 32;
|
||||
Bool reg R8 result = (*(bit_field(U32 *)) & chunk_bit) >> chunk_mod;
|
||||
|
||||
*(bit_field(U32 *)) |= chunk_bit;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue