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Document and clean E1000 defines, enable bus mastering, begin debugging TX methods.
This commit is contained in:
TomAwezome
parent
9b7a335eea
commit
a573d0efbb
1 changed files with 92 additions and 69 deletions
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@ -18,28 +18,33 @@
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#define E1000_REG_CTRL 0x0000
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#define E1000_REG_EERD 0x0014 // EEPROM Read
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#define E1000_REG_FCAL 0x0028 // Flow Control Address Low
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#define E1000_REG_FCAH 0x002C // Flow Control Address High
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#define E1000_REG_FCT 0x0030 // Flow Control Type
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#define E1000_REG_ICR 0x00C0 // Interrupt Cause Read
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#define E1000_REG_IMS 0x00D0
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#define E1000_REG_RCTL 0x0100
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#define E1000_REG_TCTL 0x0400
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#define E1000_REG_RDBAL 0x2800
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#define E1000_REG_RDBAH 0x2804
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#define E1000_REG_RDLEN 0x2808
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#define E1000_REG_RDH 0x2810
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#define E1000_REG_RDT 0x2818
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#define E1000_REG_TDBAL 0x3800
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#define E1000_REG_TDBAH 0x3804
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#define E1000_REG_TDLEN 0x3808
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#define E1000_REG_TDH 0x3810
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#define E1000_REG_TDT 0x3818
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#define E1000_REG_IMS 0x00D0 // Interrupt Mask Set/Read
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#define E1000_REG_RCTL 0x0100 // Receive Control
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#define E1000_REG_FCTTV 0x0170 // Flow Control Transmit Timer Value
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#define E1000_REG_TCTL 0x0400 // Transmit Control
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#define E1000_REG_TIPG 0x0410 // Transmit Inter Packet Gap timer
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#define E1000_REG_RDBAL 0x2800 // Receive Descriptor Base Address Low
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#define E1000_REG_RDBAH 0x2804 // Receive Descriptor Base Address High
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#define E1000_REG_RDLEN 0x2808 // Receive Descriptor Length
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#define E1000_REG_RDH 0x2810 // Receive Descriptor Head
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#define E1000_REG_RDT 0x2818 // Receive Descriptor Tail
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#define E1000_REG_TDBAL 0x3800 // Transmit Descriptor Base Address Low
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#define E1000_REG_TDBAH 0x3804 // Transmit Descriptor Base Address High
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#define E1000_REG_TDLEN 0x3808 // Transmit Descriptor Length
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#define E1000_REG_TDH 0x3810 // Transmit Descriptor Head
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#define E1000_REG_TDT 0x3818 // Transmit Descriptor Tail
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#define E1000_REG_MTA 0x5200 // Multicast Table Array
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#define E1000_REG_RAL 0x5400 // Receive Address Low
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#define E1000_REG_RAH 0x5404 // Receive Address High
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#define E1000_CTRLf_LRST 3 // Link Reset
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#define E1000_CTRLf_ASDE 5 // Auto-Speed Detection Enable
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#define E1000_CTRLf_SLU 6 // Set Link Up
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#define E1000_CTRLf_ILOS 7 // Invert Loss-Of-Signal
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#define E1000_CTRLf_RST 26 // Reset
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#define E1000_CTRLf_VME 30 // VLAN Mode Enable
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#define E1000_CTRLf_PHY_RST 31 // PHY Reset
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@ -47,47 +52,40 @@
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#define E1000_CTRLF_ASDE (1 << E1000_CTRLf_ASDE)
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#define E1000_CTRLF_SLU (1 << E1000_CTRLf_SLU)
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#define E1000_CTRLF_ILOS (1 << E1000_CTRLf_ILOS)
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#define E1000_CTRLF_RST (1 << E1000_CTRLf_RST)
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#define E1000_CTRLF_VME (1 << E1000_CTRLf_VME)
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#define E1000_CTRLF_PHY_RST (1 << E1000_CTRLf_PHY_RST)
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#define E1000_RCTLf_EN 1
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#define E1000_RCTLf_SBP 2
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#define E1000_RCTLf_UPE 3
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#define E1000_RCTLf_MPE 4
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#define E1000_RCTLf_LPE 5
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//#define E1000_RCTLf_RDMTS_HALF
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#define E1000_RCTLf_RDMTS_QUARTER 8
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#define E1000_RCTLf_RDMTS_EIGHTH 9
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#define E1000_RCTLf_BAM 15
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#define E1000_RCTLf_BSIZE_1024 16
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#define E1000_RCTLf_BSIZE_512 17
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#define E1000_RCTLf_BSIZE_256 18
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//#define E1000_RCTLf_BSIZE_2048
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//#define E1000_RCTLf_BSIZE_4096
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//#define E1000_RCTLf_BSIZE_8192
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//#define E1000_RCTLf_BSIZE_16384
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#define E1000_RCTLf_SECRC 26
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#define E1000_RCTLf_EN 1 // Receiver Enable
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#define E1000_RCTLf_SBP 2 // Store Bad Packets
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#define E1000_RCTLf_UPE 3 // Unicast Promiscuous Enabled
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#define E1000_RCTLf_MPE 4 // Multicast Promiscuous Enabled
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#define E1000_RCTLf_LPE 5 // Long Packet Reception Enable
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#define E1000_RCTLf_RDMTS 8 // Receive Descriptor Minimum Threshold Size
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#define E1000_RCTLf_BAM 15 // Broadcast Accept Mode
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#define E1000_RCTLf_BSIZE 16 // Receive Buffer Size
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#define E1000_RCTLf_SECRC 26 // Strip Ethernet CRC
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#define E1000_RCTLF_EN (1 << E1000_RCTLf_EN)
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#define E1000_RCTLF_SBP (1 << E1000_RCTLf_SBP)
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#define E1000_RCTLF_UPE (1 << E1000_RCTLf_UPE)
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#define E1000_RCTLF_MPE (1 << E1000_RCTLf_MPE)
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#define E1000_RCTLF_LPE (1 << E1000_RCTLf_LPE)
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//#define E1000_RCTLF_RDMTS_HALF
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#define E1000_RCTLF_RDMTS_QUARTER (1 << E1000_RCTLf_RDMTS_QUARTER)
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#define E1000_RCTLF_RDMTS_EIGHTH (2 << E1000_RCTLf_RDMTS_QUARTER)
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#define E1000_RCTLF_RDMTS_HALF (0 << E1000_RCTLf_RDMTS)
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#define E1000_RCTLF_RDMTS_QUARTER (1 << E1000_RCTLf_RDMTS)
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#define E1000_RCTLF_RDMTS_EIGHTH (2 << E1000_RCTLf_RDMTS)
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#define E1000_RCTLF_BAM (1 << E1000_RCTLf_BAM)
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#define E1000_RCTLF_BSIZE_1024 (1 << E1000_RCTLf_BSIZE_1024)
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#define E1000_RCTLF_BSIZE_512 (2 << E1000_RCTLf_BSIZE_1024)
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#define E1000_RCTLF_BSIZE_256 (3 << E1000_RCTLf_BSIZE_1024)
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//#define E1000_RCTLF_BSIZE_2048
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//#define E1000_RCTLF_BSIZE_4096
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//#define E1000_RCTLF_BSIZE_8192
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//#define E1000_RCTLF_BSIZE_16384
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#define E1000_RCTLF_BSIZE_2048 (0 << E1000_RCTLf_BSIZE) // when Buffer Size Extension is 0
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#define E1000_RCTLF_BSIZE_1024 (1 << E1000_RCTLf_BSIZE) // ''
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#define E1000_RCTLF_BSIZE_512 (2 << E1000_RCTLf_BSIZE) // ''
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#define E1000_RCTLF_BSIZE_256 (3 << E1000_RCTLf_BSIZE) // ''
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#define E1000_RCTLF_BSIZE_16384 (1 << E1000_RCTLf_BSIZE) // when Buffer Size Extension is 1
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#define E1000_RCTLF_BSIZE_8192 (2 << E1000_RCTLf_BSIZE) // ''
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#define E1000_RCTLF_BSIZE_4096 (3 << E1000_RCTLf_BSIZE) // ''
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#define E1000_RCTLF_SECRC (1 << E1000_RCTLf_SECRC)
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#define E1000_TCTLf_EN 1
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#define E1000_TCTLf_PSP 3
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#define E1000_TCTLf_EN 1 // Trasmit Enable
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#define E1000_TCTLf_PSP 3 // Pad Short Packets
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#define E1000_TCTLF_EN (1 << E1000_TCTLf_EN)
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#define E1000_TCTLF_PSP (1 << E1000_TCTLf_PSP)
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@ -96,7 +94,7 @@
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#define E1000_RDESC_STATUSF_EOP (1 << E1000_RDESC_STATUSf_EOP)
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#define E1000_EERDf_DONE 4
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#define E1000_EERDf_DONE 4 // Read Done
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#define E1000_EERDF_DONE (1 << E1000_EERDf_DONE)
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@ -132,19 +130,20 @@
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#define E1000_ICRF_RXO (1 << E1000_ICRf_RXO)
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#define E1000_ICRF_RXT (1 << E1000_ICRf_RXT)
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#define E1000_IMSf_TXDW 0
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#define E1000_IMSf_TXQE 1
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#define E1000_IMSf_LSC 2
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#define E1000_IMSf_RXSEQ 3
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#define E1000_IMSf_RXDMT 4
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#define E1000_IMSf_RXO 6
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#define E1000_IMSf_RXT 7
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#define E1000_IMSf_MDAC 9
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#define E1000_IMSf_RXCFG 10
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#define E1000_IMSf_PHYINT 12
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#define E1000_IMSf_GPI 13 // 13-14
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#define E1000_IMSf_TXDLOW 15
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#define E1000_IMSf_SRPD 16
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#define E1000_IMSf_TXDW 0 // Transmit Descriptor Written Back
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#define E1000_IMSf_TXQE 1 // Transmit Queue Empty
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#define E1000_IMSf_LSC 2 // Link Status Change
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#define E1000_IMSf_RXSEQ 3 // Receive Sequence Error
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#define E1000_IMSf_RXDMT 4 // Receive Descriptor Minimum Threshold Reached
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#define E1000_IMSf_RXO 6 // Receiver FIFO Overrun
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#define E1000_IMSf_RXT 7 // Receive Timer Interrupt
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#define E1000_IMSf_MDAC 9 // MDI/O Access Complete Interrupt
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#define E1000_IMSf_RXCFG 10 // Receiving /C/ ordered sets
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#define E1000_IMSf_PHYINT 12 // PHY Interrupt
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#define E1000_IMSf_GPI 13 // General Purpose Interrupts (Bits 13-14)
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// E1000_IMSf_GPI 14
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#define E1000_IMSf_TXDLOW 15 // Transmit Descriptor Low Threshold Reached
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#define E1000_IMSf_SRPD 16 // Small Receive Packet Detection
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#define E1000_IMSF_TXDW (1 << E1000_IMSf_TXDW)
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#define E1000_IMSF_TXQE (1 << E1000_IMSf_TXQE)
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@ -349,6 +348,7 @@ I64 E1000TransmitPacketAllocate(U8 **packet_buffer_out, I64 length)
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Bts(&entry->cmd, E1000_TDESC_CMDf_EOP);
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Bts(&entry->cmd, E1000_TDESC_CMDf_IFCS);
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Bts(&entry->cmd, E1000_TDESC_CMDf_RS);
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entry->sta = 0;
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NetLog("E1000 ALLOCATE TX PACKET: de_index: %X.", de_index);
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return de_index;
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@ -486,6 +486,7 @@ U0 E1000InitRX()
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{
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entry->address = e1000.rx_buffer_addr + de_index * ETHERNET_FRAME_SIZE; // is this right? might need to change ?..
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// 01000101 MAlloc's 8208 for each DE
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entry++;
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}
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// setup rx de ring buffer
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@ -512,6 +513,8 @@ U0 E1000InitRX()
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U0 E1000InitTX()
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{
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I64 de_index;
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e1000.tx_de_buffer_phys = CAllocAligned(sizeof(CE1000DescriptorEntryTX) * E1000_TX_BUFF_COUNT,
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16,
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Fs->code_heap);
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@ -522,6 +525,17 @@ U0 E1000InitTX()
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e1000.tx_buffer_addr = dev.uncached_alias + e1000.tx_buffer_addr_phys;
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// iterate de's and make packet buffers for each
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CE1000DescriptorEntryTX *entry = e1000.tx_de_buffer;
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for (de_index = 0; de_index < E1000_TX_BUFF_COUNT; de_index++)
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{
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entry->address = e1000.tx_buffer_addr + de_index * ETHERNET_FRAME_SIZE; // is this right? might need to change ?..
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entry->cmd = 0b1000;
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entry->sta = 0x1;
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// 01000101 MAlloc's 8208 for each DE
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entry++;
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}
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// setup tx de ring buffer
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E1000MMIOWrite(E1000_REG_TDBAH, e1000.tx_de_buffer >> 32); // should we be using uncached addr here ?
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E1000MMIOWrite(E1000_REG_TDBAL, e1000.tx_de_buffer & 0xFFFFFFFF);
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@ -531,10 +545,13 @@ U0 E1000InitTX()
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// set head tail pointers
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E1000MMIOWrite(E1000_REG_TDH, 0);
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E1000MMIOWrite(E1000_REG_TDT, E1000_RX_BUFF_COUNT);
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E1000MMIOWrite(E1000_REG_TDT, 0);//E1000_TX_BUFF_COUNT);
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// set transmit control reg
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E1000MMIOWrite(E1000_REG_TCTL, E1000_TCTLF_EN | E1000_TCTLF_PSP);
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// E1000MMIOWrite(E1000_REG_TCTL, 0b0110000000000111111000011111010);
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E1000MMIOWrite(E1000_REG_TIPG, 0x0060200A);
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}
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@ -551,11 +568,16 @@ U0 E1000Init()
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if (!e1000.pci)
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return; // if we don't find the card, quit.
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// enable PCI bus master, memory space access, I/O space access
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PCIWriteU16(e1000.pci->bus, e1000.pci->dev, e1000.pci->fun, PCIR_COMMAND, 0x7);
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e1000.mmio_address = dev.uncached_alias + e1000.pci->base[0] & ~0xF;
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// Assuming card supports MMIO... lower 4 bits are hardwired zero (?)
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"\nMMIO address: 0x%0X\n", e1000.mmio_address;
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E1000MMIOWrite(E1000_REG_CTRL, E1000MMIORead(E1000_REG_CTRL) | E1000_CTRLF_RST);
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Sleep(1);
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val = E1000MMIORead(E1000_REG_CTRL);
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val |= E1000_CTRLF_SLU | E1000_CTRLF_ASDE;
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val &= ~(E1000_CTRLF_LRST | E1000_CTRLF_PHY_RST | E1000_CTRLF_ILOS | E1000_CTRLF_VME);
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@ -572,12 +594,13 @@ U0 E1000Init()
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E1000MMIOWrite(E1000_REG_RAL, val);
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val = 0;
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MemCopy(&val, e1000.mac_address + 4, 2);
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E1000MMIOWrite(E1000_REG_RAH, val | E1000_RAHF_AV);
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E1000MMIOWrite(E1000_REG_RAH, val | E1000_RAHF_AV);
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// set flow control registers
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E1000MMIOWrite(0x28, 0x00C28001);
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E1000MMIOWrite(0x2C, 0x00000100);
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E1000MMIOWrite(0x30, 0x8808);
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E1000MMIOWrite(E1000_REG_FCAL, 0);
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E1000MMIOWrite(E1000_REG_FCAH, 0);
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E1000MMIOWrite(E1000_REG_FCT, 0);
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E1000MMIOWrite(E1000_REG_FCTTV, 0);
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// enable & clear existing interupts
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E1000MMIOWrite(E1000_REG_IMS, E1000_IMSF_LSC |
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@ -655,4 +678,4 @@ U0 NetStart()
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}
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E1000Init;
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E1000Init;
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