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Clean up E1000 PCI register init.
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1 changed files with 20 additions and 3 deletions
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@ -16,6 +16,16 @@
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// TODO: clean up entire driver
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// TODO: clean up entire driver
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#define E1000_CMDf_IOEN 0
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#define E1000_CMDf_MAEN 1
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#define E1000_CMDf_BMEN 2
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#define E1000_CMDf_MWEN 4
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#define E1000_CMDF_IOEN (1 << E1000_CMDf_IOEN)
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#define E1000_CMDF_MAEN (1 << E1000_CMDf_MAEN)
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#define E1000_CMDF_BMEN (1 << E1000_CMDf_BMEN)
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#define E1000_CMDF_MWEN (1 << E1000_CMDf_MWEN)
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#define E1000_REG_CTRL 0x0000
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#define E1000_REG_CTRL 0x0000
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#define E1000_REG_EERD 0x0014 // EEPROM Read
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#define E1000_REG_EERD 0x0014 // EEPROM Read
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#define E1000_REG_FCAL 0x0028 // Flow Control Address Low
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#define E1000_REG_FCAL 0x0028 // Flow Control Address Low
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@ -568,8 +578,15 @@ U0 E1000Init()
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if (!e1000.pci)
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if (!e1000.pci)
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return; // if we don't find the card, quit.
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return; // if we don't find the card, quit.
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// enable PCI bus master, memory space access, I/O space access
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/* Clear command register of E1000 PCI device,
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PCIWriteU16(e1000.pci->bus, e1000.pci->dev, e1000.pci->fun, PCIR_COMMAND, 0x7);
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set IO Enable, Bus Master Enable,
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Memory Access Enable, and
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Memory Write & Invalidate Enable bits. */
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PCIWriteU16(e1000.pci->bus,
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e1000.pci->dev,
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e1000.pci->fun,
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PCIR_COMMAND,
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E1000_CMDF_IOEN | E1000_CMDF_BMEN | E1000_CMDF_MAEN | E1000_CMDF_MWEN);
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e1000.mmio_address = dev.uncached_alias + e1000.pci->base[0] & ~0xF;
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e1000.mmio_address = dev.uncached_alias + e1000.pci->base[0] & ~0xF;
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// Assuming card supports MMIO... lower 4 bits are hardwired zero (?)
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// Assuming card supports MMIO... lower 4 bits are hardwired zero (?)
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@ -678,4 +695,4 @@ U0 NetStart()
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}
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}
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E1000Init;
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E1000Init;
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