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https://github.com/Zeal-Operating-System/ZealOS.git
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Merge pull request #79 from tinkeros/misc-pcnet-fixes
Fix driver uncached alias and Bt function usage
This commit is contained in:
TomAwezome
GitHub
commit
777203d952
1 changed files with 63 additions and 53 deletions
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@ -13,11 +13,6 @@
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- Clear documentation.
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*/
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//#define PCNET_DEVICE_ID 0x2000
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//#define PCNET_VENDOR_ID 0x1022
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//#define PCI_REG_COMMAND 0x04
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#define PCNET_CMDf_IOEN 0
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#define PCNET_CMDf_BMEN 2
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@ -65,7 +60,9 @@
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#define PCNET_CTRL_INIT 0
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#define PCNET_CTRL_STRT 1
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#define PCNET_CTRL_STOP 2
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#define PCNET_CTRL_RINT 10
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#define PCNET_CTRL_IENA 6
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#define PCNET_CTRL_IDON 8
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#define PCNET_CTRL_RINT 10
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#define PCNET_RX_BUFF_COUNT 32 // Linux & Shrine Driver use 32 and 8 for
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#define PCNET_TX_BUFF_COUNT 8 // these, we could allow more if wanted.
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@ -88,8 +85,6 @@ class CPCNet
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U8 *rx_de_buffer_phys; // Pointer to the buffer of RX Descriptor Entries. (Code Heap, lower 2Gb)
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U8 *tx_de_buffer_phys; // Pointer to the buffer of TX Descriptor Entries. (Code Heap, lower 2Gb)
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U32 rx_buffer_addr; // Uncached-alias of address of receive buffers.
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U32 tx_buffer_addr; // Uncached-alias of address of transmit buffers.
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U32 rx_buffer_addr_phys; // Physical address of actual receive buffers (< 4 Gb)
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U32 tx_buffer_addr_phys; // Physical address of actual transmit buffers (< 4 Gb)
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@ -199,7 +194,7 @@ U0 PCNetSWStyleSet()
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csr &= ~0xFF; // clears first 8 bits: SWSTYLE 8-bit register.
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csr |= PCNET_SWSTYLE_SELECTION; // set SWSTYLE to PCNet-PCI mode.
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PCIBts(&csr, PCNET_SWSTYLE_SSIZE32); // set SSIZE32 bit 1
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Bts(&csr, PCNET_SWSTYLE_SSIZE32); // set SSIZE32 bit 1
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PCNetCSRWrite(PCNET_CSR_SOFTWARESTYLE, csr);
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}
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@ -271,14 +266,11 @@ U0 PCNetBuffersAllocate()
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//Shrine does a check and returns -1 here, if the end of either buffer exceeds 0x100000000
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pcnet.rx_buffer_addr = dev.uncached_alias + pcnet.rx_buffer_addr_phys;
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pcnet.tx_buffer_addr = dev.uncached_alias + pcnet.tx_buffer_addr_phys;
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CPCNetDescriptorEntry *entry = pcnet.rx_de_buffer;
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for (de_index = 0; de_index < PCNET_RX_BUFF_COUNT; de_index++)
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{
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PCNetDescriptorEntryInit(&entry[de_index],
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pcnet.rx_buffer_addr + de_index * ETHERNET_FRAME_SIZE,
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pcnet.rx_buffer_addr_phys + de_index * ETHERNET_FRAME_SIZE,
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TRUE); // TRUE for is_rx.
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}
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@ -286,7 +278,7 @@ U0 PCNetBuffersAllocate()
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for (de_index = 0; de_index < PCNET_TX_BUFF_COUNT; de_index++)
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{
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PCNetDescriptorEntryInit(&entry[de_index],
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pcnet.tx_buffer_addr + de_index * ETHERNET_FRAME_SIZE,
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pcnet.tx_buffer_addr_phys + de_index * ETHERNET_FRAME_SIZE,
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FALSE); // FALSE for is_rx.
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}
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}
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@ -343,11 +335,11 @@ U0 PCNetDirectInit()
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Bitshift right of 16 will replace
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first 16 bits with upper 16 bits,
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remaining bits cleared.*/
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PCNetCSRWrite(PCNET_CSR_BADRL, pcnet.rx_buffer_addr & 0xFFFF);
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PCNetCSRWrite(PCNET_CSR_BADRU, pcnet.rx_buffer_addr >> 16);
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PCNetCSRWrite(PCNET_CSR_BADRL, pcnet.rx_buffer_addr_phys & 0xFFFF);
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PCNetCSRWrite(PCNET_CSR_BADRU, pcnet.rx_buffer_addr_phys >> 16);
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PCNetCSRWrite(PCNET_CSR_BADTL, pcnet.tx_buffer_addr & 0xFFFF);
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PCNetCSRWrite(PCNET_CSR_BADTU, pcnet.tx_buffer_addr >> 16);
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PCNetCSRWrite(PCNET_CSR_BADTL, pcnet.tx_buffer_addr_phys & 0xFFFF);
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PCNetCSRWrite(PCNET_CSR_BADTU, pcnet.tx_buffer_addr_phys >> 16);
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/* AMD PCNet datasheet p. 1-967
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Default value at hardware init is
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@ -399,11 +391,11 @@ U0 PCNetInterruptCSRSet()
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U32 csr = PCNetCSRRead(PCNET_CSR_INTERRUPTS);
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PCIBtr(&csr, PCNET_INT_BSWP);
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PCIBtr(&csr, PCNET_INT_RINTM);
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Btr(&csr, PCNET_INT_BSWP);
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Btr(&csr, PCNET_INT_RINTM);
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PCIBts(&csr, PCNET_INT_IDONM);
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PCIBts(&csr, PCNET_INT_TINTM);
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Bts(&csr, PCNET_INT_IDONM);
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Bts(&csr, PCNET_INT_TINTM);
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PCNetCSRWrite(PCNET_CSR_INTERRUPTS, csr);
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}
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@ -416,7 +408,7 @@ U0 PCNetTXAutoPadEnable()
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U32 csr = PCNetCSRRead(PCNET_CSR_FEATURECTRL);
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PCIBts(&csr, PCNET_FEATURE_APADXMT);
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Bts(&csr, PCNET_FEATURE_APADXMT);
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PCNetCSRWrite(PCNET_CSR_FEATURECTRL, csr);
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}
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@ -431,14 +423,33 @@ U0 PCNetConfigModeExit()
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U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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PCIBtr(&csr, PCNET_CTRL_INIT);
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PCIBtr(&csr, PCNET_CTRL_STOP);
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Btr(&csr, PCNET_CTRL_INIT);
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Btr(&csr, PCNET_CTRL_STOP);
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PCIBts(&csr, PCNET_CTRL_STRT);
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Bts(&csr, PCNET_CTRL_STRT);
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PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
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}
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U0 PCNetUploadConfig()
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{/* Upload new config and wait for card to acknowlege */
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U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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Bts(&csr, PCNET_CTRL_INIT);
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Bts(&csr, PCNET_CTRL_IENA);
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PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
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Btr(&csr, PCNET_CTRL_IDON);
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while (!Bt(&csr, PCNET_CTRL_IDON))
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{
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Yield;
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csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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}
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}
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I64 PCNetDriverOwns(CPCNetDescriptorEntry* entry)
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{/* Returns whether the value of the OWN bit of the
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Descriptor Entry is zero. If 0, driver owns,
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@ -495,9 +506,7 @@ I64 PCNetTransmitPacketAllocate(U8 **packet_buffer_out, I64 length)
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pcnet.current_tx_de_index = (pcnet.current_tx_de_index + 1) & (PCNET_TX_BUFF_COUNT - 1);
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*packet_buffer_out = pcnet.tx_buffer_addr + de_index * ETHERNET_FRAME_SIZE;
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MemSet(*packet_buffer_out, 0, ETHERNET_FRAME_SIZE); // Clear buffer contents in advance.
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*packet_buffer_out = pcnet.tx_buffer_addr_phys + de_index * ETHERNET_FRAME_SIZE;
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NetLog("PCNET ALLOCATE TX PACKET: de_index: %X.", de_index);
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return de_index;
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@ -543,7 +552,7 @@ I64 PCNetPacketReceive(U8 **packet_buffer_out, U16 *packet_length_out)
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pcnet.current_rx_de_index = (pcnet.current_rx_de_index + 1) & (PCNET_RX_BUFF_COUNT - 1);
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NetDebug("PCNET RECEIVE PACKET: de_index incremented = 0x%0X", pcnet.current_rx_de_index);
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*packet_buffer_out = pcnet.rx_buffer_addr + de_index * ETHERNET_FRAME_SIZE;
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*packet_buffer_out = pcnet.rx_buffer_addr_phys + de_index * ETHERNET_FRAME_SIZE;
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*packet_length_out = packet_length;
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return de_index;
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@ -584,11 +593,12 @@ interrupt U0 PCNetIRQ()
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if (de_index >= 0) // todo: necessary? check increment logic in PCNetPacketReceive.
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{
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NetLog("PCNET IRQ: Pushing copy into Net Queue, releasing receive packet.");
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NetQueuePush(packet_buffer, packet_length);
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// uncached read
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NetQueuePush(packet_buffer + dev.uncached_alias, packet_length);
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PCNetReceivePacketRelease(de_index);
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}
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PCIBts(&csr, PCNET_CTRL_RINT);
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Bts(&csr, PCNET_CTRL_RINT);
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PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
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@ -651,10 +661,10 @@ U0 PCNetInit()
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PCNet32BitModeEnable;
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U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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NetLog("PCNET INIT START: what is INIT ?: %d", PCIBt(&csr, PCNET_CTRL_INIT));
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NetLog("PCNET INIT START: what is STRT ?: %d", PCIBt(&csr, PCNET_CTRL_STRT));
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NetLog("PCNET INIT START: what is STOP ?: %d", PCIBt(&csr, PCNET_CTRL_STOP));
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NetLog("PCNET INIT START: what is RINT ?: %d", PCIBt(&csr, PCNET_CTRL_RINT));
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NetLog("PCNET INIT START: what is INIT ?: %d", Bt(&csr, PCNET_CTRL_INIT));
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NetLog("PCNET INIT START: what is STRT ?: %d", Bt(&csr, PCNET_CTRL_STRT));
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NetLog("PCNET INIT START: what is STOP ?: %d", Bt(&csr, PCNET_CTRL_STOP));
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NetLog("PCNET INIT START: what is RINT ?: %d", Bt(&csr, PCNET_CTRL_RINT));
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PCNetSWStyleSet;
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@ -671,31 +681,28 @@ U0 PCNetInit()
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PCNetTXAutoPadEnable;
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PCNetCSRWrite(0, PCNetCSRRead(0) | 1 | 1 << 6); // ?
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PCNetUploadConfig;
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csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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NetLog("PCNET INIT UPLOAD: what is INIT ?: %d", PCIBt(&csr, PCNET_CTRL_INIT));
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NetLog("PCNET INIT UPLOAD: what is STRT ?: %d", PCIBt(&csr, PCNET_CTRL_STRT));
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NetLog("PCNET INIT UPLOAD: what is STOP ?: %d", PCIBt(&csr, PCNET_CTRL_STOP));
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NetLog("PCNET INIT UPLOAD: what is RINT ?: %d", PCIBt(&csr, PCNET_CTRL_RINT));
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while (!(PCNetCSRRead(0) & 1 << 8)) // ?
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Yield;
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NetLog("PCNET INIT UPLOAD: what is INIT ?: %d", Bt(&csr, PCNET_CTRL_INIT));
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NetLog("PCNET INIT UPLOAD: what is STRT ?: %d", Bt(&csr, PCNET_CTRL_STRT));
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NetLog("PCNET INIT UPLOAD: what is STOP ?: %d", Bt(&csr, PCNET_CTRL_STOP));
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NetLog("PCNET INIT UPLOAD: what is RINT ?: %d", Bt(&csr, PCNET_CTRL_RINT));
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PCNetConfigModeExit;
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Sleep(100); //? necessary?
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csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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NetLog("PCNET INIT END: what is INIT ?: %d", PCIBt(&csr, PCNET_CTRL_INIT));
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NetLog("PCNET INIT END: what is STRT ?: %d", PCIBt(&csr, PCNET_CTRL_STRT));
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NetLog("PCNET INIT END: what is STOP ?: %d", PCIBt(&csr, PCNET_CTRL_STOP));
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NetLog("PCNET INIT END: what is RINT ?: %d", PCIBt(&csr, PCNET_CTRL_RINT));
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NetLog("PCNET INIT END: what is TXON ?: %d", PCIBt(&csr, 4));
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NetLog("PCNET INIT END: what is RXON ?: %d", PCIBt(&csr, 5));
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NetLog("PCNET INIT END: what is INIT ?: %d", Bt(&csr, PCNET_CTRL_INIT));
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NetLog("PCNET INIT END: what is STRT ?: %d", Bt(&csr, PCNET_CTRL_STRT));
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NetLog("PCNET INIT END: what is STOP ?: %d", Bt(&csr, PCNET_CTRL_STOP));
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NetLog("PCNET INIT END: what is RINT ?: %d", Bt(&csr, PCNET_CTRL_RINT));
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NetLog("PCNET INIT END: what is TXON ?: %d", Bt(&csr, 4));
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NetLog("PCNET INIT END: what is RXON ?: %d", Bt(&csr, 5));
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csr = PCNetCSRRead(PCNET_CSR_POLLINT);
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NetLog("PCNET INIT END: what is POLLINT ?: %d", PCIBt(&csr, PCNET_CTRL_RINT));
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NetLog("PCNET INIT END: what is POLLINT ?: %d", Bt(&csr, PCNET_CTRL_RINT));
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NetLog("PCNET INIT END: Redirecting interrupts.");
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PCNetInterruptsSetup;
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@ -726,6 +733,7 @@ I64 EthernetFrameAllocate(U8 **packet_buffer_out,
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}
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de_index = PCNetTransmitPacketAllocate(ðernet_frame, ETHERNET_MAC_HEADER_LENGTH + packet_length);
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ethernet_frame += dev.uncached_alias; // Make write uncached
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if (de_index < 0)
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{
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@ -733,6 +741,8 @@ I64 EthernetFrameAllocate(U8 **packet_buffer_out,
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return -1; // Positive value expected. Functions calling this must factor this in.
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}
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MemSet(ethernet_frame, 0, ETHERNET_FRAME_SIZE); // Clear buffer contents in advance.
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MemCopy(ethernet_frame, destination_address, MAC_ADDRESS_LENGTH);
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MemCopy(ethernet_frame + MAC_ADDRESS_LENGTH, source_address, MAC_ADDRESS_LENGTH);
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@ -753,7 +763,7 @@ U0 NetStop()
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{ // Halt network activity by setting STOP bit on Status CSR.
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U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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PCIBts(&csr, PCNET_CTRL_STOP);
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Bts(&csr, PCNET_CTRL_STOP);
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PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
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@ -763,7 +773,7 @@ U0 NetStart()
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{ // Continue network activity. Setting START bit clears STOP/INIT.
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U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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PCIBts(&csr, PCNET_CTRL_STRT);
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Bts(&csr, PCNET_CTRL_STRT);
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PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
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}
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