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Change SSE MOVSD opcode configuration.

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This commit is contained in:
TomAwezome 2021-12-12 00:57:06 -05:00
parent 38ae0c07c2
commit 7521710585
1 changed files with 7 additions and 3 deletions
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10
src/Compiler/OpCodes.DD
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@ -278,8 +278,12 @@ OPCODE MOVSS
0xF3 0x0F 0x10,/R XMM XMM128 0xF3 0x0F 0x10,/R XMM XMM128
0xF3 0x0F 0x11,/R XMM128 XMM; 0xF3 0x0F 0x11,/R XMM128 XMM;
OPCODE MOVSD_SSE OPCODE MOVSD_SSE
0xF2 0x0F 0x10,/R XMM XMM64 0xF2 0x0F 0x10,/R XMM XMM128 // 2nd arg kludge
0xF2 0x0F 0x11,/R XMM64 XMM; 0xF2 0x0F 0x10,/R XMM M64
0xF2 0x0F 0x11,/R M64 XMM;
// 0xF2 0x0F 0x11,/R XMM64 XMM;
// 0xF2 0x0F 0x10,/R XMM XMM64
// 0xF2 0x0F 0x11,/R XMM64 XMM;
OPCODE MOVD OPCODE MOVD
0x66 0x0F 0x6E,/R XMM RM32 0x66 0x0F 0x6E,/R XMM RM32
0x66 0x0F 0x7E,/R RM32 XMM; 0x66 0x0F 0x7E,/R RM32 XMM;
@ -1616,4 +1620,4 @@ OPCODE MOV_RAX_CR3 0x0F 0x20 0xD8, 32=;
OPCODE MOV_CR4_RAX 0x0F 0x22 0xE0, 32=; OPCODE MOV_CR4_RAX 0x0F 0x22 0xE0, 32=;
OPCODE MOV_RAX_CR4 0x0F 0x20 0xE0, 32=; OPCODE MOV_RAX_CR4 0x0F 0x20 0xE0, 32=;
//OPCODE MULPD 0x66 0x0F 0x59,/R XMM XMM; //OPCODE MULPD 0x66 0x0F 0x59,/R XMM XMM;