mirror of
https://github.com/Zeal-Operating-System/ZealOS.git
synced 2024-12-24 22:50:28 +00:00
Merge branch 'master' into master
This commit is contained in:
TomAwezome
GitHub
commit
645f383a9f
6 changed files with 77 additions and 10 deletions
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@ -1,4 +1,8 @@
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$WW,1$$FG,5$$TX+CX,"ChangeLog"$$FG$
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$IV,1$----12/21/22 03:38:35----$IV,0$
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* Raised version number to 2.01.
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* Created $LK+PU,"FreeAll",A="MN:FreeAll"$ method to /Kernel/Memory/MAllocFree.ZC and extern to $LK+PU,"/Kernel/KernelC.HH",A="FF:::/Kernel/KernelC.HH,FreeAll"$.
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$IV,1$----11/02/22 20:26:55----$IV,0$
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* Raised version number to 2.00.
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* Updated the $LK,"Charter",A="FI:::/Doc/Charter.DD"$ to allow non-Public-Domain MBR/UEFI bootloaders, as long as the Public Domain ZealOS HDD/DVD Boot Loaders are included, offered, and functional. The Charter upholds that all operating system code must still be 100% public domain. Updated $LK+PU,"Credits",A="FI:::/Doc/Credits.DD"$, $LK+PU,"FAQ",A="FI:::/Doc/FAQ.DD"$, $LK+PU,"Features.DD",A="FI:::/Doc/Features.DD"$, $LK+PU,"Welcome.DD",A="FI:::/Doc/Welcome.DD"$.
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@ -23,8 +23,12 @@
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#define PCNET_DW_RDP 0x10
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#define PCNET_DW_RAP 0x14
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#define PCNET_DW_BDP 0x1C
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#define PCNET_DW_RESET 0x18 // reset reg location when card is in 32-bit mode
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#define PCNET_BCR_MISC_CONFIG 2
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#define PCNET_BCR_FULL_DUPLEX_CTRL 9
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#define PCNET_CSR_CTRLSTATUS 0
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#define PCNET_CSR_INTERRUPTS 3
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#define PCNET_CSR_FEATURECTRL 4
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@ -57,6 +61,11 @@
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#define PCNET_FEATURE_APADXMT 11
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#define PCNET_BCR_MISC_CONFIG_ASEL 1
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#define PCNET_BCR_FULL_DUPLEX_CTRL_FDEN 0
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#define PCNET_BCR_FULL_DUPLEX_CTRL_AUIFD 1
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#define PCNET_CTRL_INIT 0
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#define PCNET_CTRL_STRT 1
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#define PCNET_CTRL_STOP 2
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@ -159,6 +168,28 @@ U0 PCNetRAPWrite(U32 value)
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OutU32(PCNetIOBaseGet + PCNET_DW_RAP, value);
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}
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U0 PCNetBCRWrite(U32 bcr, U32 value)
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{/* AMD PCNet datasheet p. 1-952
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Summary: Bus Control Registers are
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accessed via the BDP (Bus Data Port).
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Which BCR is selected is based on the value
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in the RAP. */
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PCNetRAPWrite(bcr);
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OutU32(PCNetIOBaseGet + PCNET_DW_BDP, value);
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}
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U32 PCNetBCRRead(U32 bcr)
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{/* AMD PCNet datasheet p. 1-952
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Summary: Bus Control Registers are
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accessed via the BDP (Bus Data Port).
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Which BCR is selected is based on the value
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in the RAP. */
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PCNetRAPWrite(bcr);
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return InU32(PCNetIOBaseGet + PCNET_DW_BDP);
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}
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U0 PCNetCSRWrite(U32 csr, U32 value)
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{/* AMD PCNet datasheet p. 1-952
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Summary: Control and Status Registers are
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@ -181,6 +212,26 @@ U32 PCNetCSRRead(U32 csr)
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return InU32(PCNetIOBaseGet + PCNET_DW_RDP);
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}
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U0 PCNetAutoLinkSelect()
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{
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U32 bcr = PCNetCSRRead(PCNET_BCR_FULL_DUPLEX_CTRL);
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Bts(&bcr, PCNET_BCR_FULL_DUPLEX_CTRL_FDEN);
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Bts(&bcr, PCNET_BCR_FULL_DUPLEX_CTRL_AUIFD);
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PCNetBCRWrite(PCNET_BCR_FULL_DUPLEX_CTRL, bcr);
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}
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U0 PCNetEnableFullDuplex()
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{
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U32 bcr = PCNetCSRRead(PCNET_BCR_MISC_CONFIG);
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Bts(&bcr, PCNET_BCR_MISC_CONFIG_ASEL);
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PCNetBCRWrite(PCNET_BCR_MISC_CONFIG, bcr);
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}
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U0 PCNetSWStyleSet()
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{/* AMD PCNet datasheet p. 1-968
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In CSR58 (Software Style), the 8-bit
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@ -260,9 +311,9 @@ U0 PCNetBuffersAllocate()
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pcnet.rx_de_buffer = dev.uncached_alias + pcnet.rx_de_buffer_phys; // we want uncached
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pcnet.tx_de_buffer = dev.uncached_alias + pcnet.tx_de_buffer_phys; // access to these.
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pcnet.rx_buffer_addr_phys = CAlloc(ETHERNET_FRAME_SIZE * PCNET_RX_BUFF_COUNT, Fs->code_heap);
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pcnet.rx_buffer_addr_phys = CAllocAligned(ETHERNET_FRAME_SIZE * PCNET_RX_BUFF_COUNT, 16, Fs->code_heap);
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pcnet.tx_buffer_addr_phys = CAlloc(ETHERNET_FRAME_SIZE * PCNET_TX_BUFF_COUNT, Fs->code_heap);
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pcnet.tx_buffer_addr_phys = CAllocAligned(ETHERNET_FRAME_SIZE * PCNET_TX_BUFF_COUNT, 16, Fs->code_heap);
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//Shrine does a check and returns -1 here, if the end of either buffer exceeds 0x100000000
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@ -361,7 +412,7 @@ U0 PCNetDirectInit()
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U8 *PCNetInitBlockSetup()
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{
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U8 *setup = CAlloc(sizeof(CPCNetBufferSetup), Fs->code_heap);
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U8 *setup = CAllocAligned(sizeof(CPCNetBufferSetup), 16, Fs->code_heap);
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CPCNetBufferSetup *u_setup = setup + dev.uncached_alias;
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U32 p_setup;
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@ -426,6 +477,7 @@ U0 PCNetConfigModeExit()
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Btr(&csr, PCNET_CTRL_INIT);
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Btr(&csr, PCNET_CTRL_STOP);
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Bts(&csr, PCNET_CTRL_IENA);
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Bts(&csr, PCNET_CTRL_STRT);
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PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
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@ -433,10 +485,9 @@ U0 PCNetConfigModeExit()
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U0 PCNetUploadConfig()
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{/* Upload new config and wait for card to acknowlege */
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U32 csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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U32 csr = 0;
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Bts(&csr, PCNET_CTRL_INIT);
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Bts(&csr, PCNET_CTRL_IENA);
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PCNetCSRWrite(PCNET_CSR_CTRLSTATUS, csr);
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@ -449,7 +500,6 @@ U0 PCNetUploadConfig()
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}
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}
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I64 PCNetDriverOwns(CPCNetDescriptorEntry* entry)
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{/* Returns whether the value of the OWN bit of the
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Descriptor Entry is zero. If 0, driver owns,
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@ -681,6 +731,10 @@ U0 PCNetInit()
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PCNetTXAutoPadEnable;
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PCNetAutoLinkSelect;
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PCNetEnableFullDuplex;
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PCNetUploadConfig;
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csr = PCNetCSRRead(PCNET_CSR_CTRLSTATUS);
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@ -13,7 +13,7 @@ CTask *sys_winmgr_task,
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U8 *rev_bits_table; //Table with U8 bits reversed
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CDate local_time_offset;
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F64 *pow10_I64,
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sys_os_version = 2.00;
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sys_os_version = 2.01;
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CAutoCompleteDictGlobals acd;
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CAutoCompleteGlobals ac;
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@ -555,6 +555,7 @@ public extern U8 *ReAlloc( U8 *src, U64 size, CTask *mem_task=NU
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public _extern _MHEAP_CTRL CHeapCtrl *MHeapCtrl( U8 *src);
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public _extern _MSIZE I64 MSize( U8 *src); //size of heap object
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public _extern _MSIZE2 I64 MSize2( U8 *src); //Internal size
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public extern U0 FreeAll(...); //Free all pointers passed
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#help_index "Memory/HeapCtrl"
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public extern U0 HeapCtrlDel( CHeapCtrl *hc);
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@ -735,4 +736,4 @@ public extern F64 tS(); //From SysTimerFreq.
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#help_index "Windows"
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public extern Bool WinInside(I64 x, I64 y, CTask *task=NULL, I64 border=0);
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#help_index ""
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#help_index ""
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@ -504,3 +504,11 @@ U8 *SysStrNew(U8 *buf)
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{//Alloc copy of string in System task's heap.
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return StrNew(buf, sys_task);
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}
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U0 FreeAll(...)
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{// Free all pointers passed
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U64 cur_arg = 0;
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while (argc--)
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Free(argv[cur_arg++]);
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}
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@ -15,8 +15,8 @@ U0 LoadDocDefines()
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//$LK,"DD_BOOT_HIGH_LOC_DVD",A="FF:::/System/Boot/BootDVD.ZC,DD_BOOT_HIGH_LOC_DVD"$
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$TR,"LineRep"$
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$ID,2$DefinePrint("DD_ZEALOS_LOC","98,675");
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$ID,-2$
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$ID,2$DefinePrint("DD_ZEALOS_LOC","98,709");
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$ID,-2$
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DefinePrint("DD_MP_VECT", "%08X", MP_VECT_ADDR);
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DefinePrint("DD_MP_VECT_END", "%08X", MP_VECT_ADDR + COREAP_16BIT_INIT_END - COREAP_16BIT_INIT - 1);
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