PIC# -> PIC_#, PIT# -> PIT_#

src/Doc/ChangeLog.DD

@@ -1,4 +1,10 @@
 $WW,1$$FG,5$$TX+CX,"ChangeLog"$$FG$
+$IV,1$----04/10/20 07:44:08----$IV,0$
+* $LK,"R",A="MN:R"$("PIC1", "$LK,"PIC_1",A="MN:PIC_1"$");
+* $LK,"R",A="MN:R"$("PIC2", "$LK,"PIC_2",A="MN:PIC_2"$");
+* $LK,"R",A="MN:R"$("PIT0", "$LK,"PIT_0",A="MN:PIT_0"$");
+* $LK,"R",A="MN:R"$("PIT2", "$LK,"PIT_2",A="MN:PIT_2"$");
+
 $IV,1$----04/09/20 19:33:16----$IV,0$
 * Added $LK,"Chess",A="FI:::/Demo/Games/Chess.CC"$ game from Sup1 disc.
 * $LK,"R",A="MN:R"$("ScanFlags", "$LK,"FlagsScan",A="MN:FlagsScan"$");
@@ -142,7 +148,7 @@ $BK,1$* Zenith 1.0 released.$BK,0$
 * Removed the unpolished HPET implementation from the kernel.
 * $LK,"Enabled the execution of SSE instructions",A="FF:::/Kernel/KStart64.CC,CR4f_OSFXSR"$. No actual SSE implementation in assembler yet, however.
 * Added definitions for the $MA-X+PU,"various flags",LM="F(\"CR0F_\", \"+lb\");F(\"CR4F_\", \"+lb\");View;"$ in the Control Registers.
-* Added definitions for the $MA-X+PU,"PIT",LM="F(\"PIT0\", \"+l-i\");F(\"PIT2\",\"+l-i\");F(\"PIT_CMD\");View;"$, and a $LK,"document",A="FI:::/Doc/PIT.DD"$ describing its usage in the OS.
+* Added definitions for the $MA-X+PU,"PIT",LM="F(\"PIT_0\", \"+l-i\");F(\"PIT_2\",\"+l-i\");F(\"PIT_CMD\");View;"$, and a $LK,"document",A="FI:::/Doc/PIT.DD"$ describing its usage in the OS.
 * Added definition for the $MA-X+PU,"PC speaker",LM="F(\"PCSPKR\");View;"$.
 * Added definitions for the $MA-X+PU,"PIC",LM="F(\"PIC\",\"-i+lb\");View;"$.
 * Added $LK,"TimeSet",A="MN:TimeSet"$() as there was no way to set the hardware clock before.

src/Doc/Comm.CC

@@ -46,14 +46,14 @@ interrupt U0 IRQComm3()
 {
 	CommHandler(2);
 	CommHandler(4);
-	OutU8(PIC1,PIC_EOI);
+	OutU8(PIC_1,PIC_EOI);
 }
 
 interrupt U0 IRQComm4()
 {
 	CommHandler(1);
 	CommHandler(3);
-	OutU8(PIC1,PIC_EOI);
+	OutU8(PIC_1,PIC_EOI);
 }
 
 U0 CommInit()
@@ -93,7 +93,7 @@ public CComm *CommInit8n1(I64 port,I64 baud)
 	OutU8(c->base+UART_MCR,4);
 	OutU8(c->base+UART_IER,0);		//Disable all IRQ
 	OutU8(c->base+UART_MCR,0xA);	//out2 and rts
-	OutU8(PIC1_DATA,InU8(PIC1_DATA) & (0xFF-0x18));//Enable 8259 IRQ 3 & 4
+	OutU8(PIC_1_DATA,InU8(PIC_1_DATA) & (0xFF-0x18));//Enable 8259 IRQ 3 & 4
 	OutU8(c->base+UART_IER,1);		//RX but no THR empty
 	POPFD
 

src/Doc/PIT.DD

@@ -2,11 +2,11 @@ $WW,1$The $FG,2$Programmable Interval Timer$FG$ has two purposes: Generate inter
 
 It has 3 channels:
 
-$LK,"Channel 0",A="MN:PIT0"$ can generate an interrupt, IRQ 0, at a defined frequency. We set it up in $LK,"TimerInit",A="MN:TimerInit"$(), and use it in $LK,"SysTimerRead",A="MN:SysTimerRead"$().
+$LK,"Channel 0",A="MN:PIT_0"$ can generate an interrupt, IRQ 0, at a defined frequency. We set it up in $LK,"TimerInit",A="MN:TimerInit"$(), and use it in $LK,"SysTimerRead",A="MN:SysTimerRead"$().
 
 Channel 1 was used historically to refresh the DRAM, but now it is obsolete as the hardware does this itself.  Channel 1 is useless and might not even be implemented anymore on modern machines.
 
-$LK,"Channel 2",A="MN:PIT2"$'s output is connected to the PC speaker.
+$LK,"Channel 2",A="MN:PIT_2"$'s output is connected to the PC speaker.
 
 The Command port is used to control each of these 3 channels. The relevant $LK,"flags",A="MN:PIT_CMDF_OPMODE_RATE_GEN"$ are defined.
 

src/Home/DoDistro.CC

@@ -1,6 +1,6 @@
 //Make Your own Distro by #include-ing this file.
 
-#define STD_DISTRO_DVD_CONFIG 	"TB\nScale2Mem(2048,0x40000)\nT \n\n1024\n768\n\n\n"
+#define STD_DISTRO_DVD_CONFIG 	"TB\nScale2Mem(2048,0x40000)\nT \n\n640\n480\n\n\n"
 
 U0 MakeMyISO(U8 *_out_iso_filename)
 {//Does everything with current drive.

src/Home/Test.CC

@@ -0,0 +1,19 @@
+U0 (*fp_test)();
+
+interrupt U0 Test()
+{
+	"nigger\n";
+}
+
+U0 Main()
+{
+	IntEntrySet(I_USER, &Test);
+
+	INT I_USER
+
+	fp_test = IntEntryGet(I_USER);
+
+	U(fp_test);
+}
+
+Main;

src/Kernel/KInterrupts.CC

@@ -128,22 +128,22 @@ U8 *IntEntrySet(I64 irq,U0 (*fp_new_handler)(),I64 type=IDTET_IRQ,I64 dpl=0)
 
 U0 IntsInit()
 {//Init 8259
-	OutU8(PIC1,0x11); //IW1
-	OutU8(PIC2,0x11); //IW1
-	OutU8(PIC1_DATA,0x20); //IW2
-	OutU8(PIC2_DATA,0x28); //IW2
-	OutU8(PIC1_DATA,0x04); //IW3
-	OutU8(PIC2_DATA,0x02); //IW3
-	OutU8(PIC1_DATA,0x0D); //IW4
-	OutU8(PIC2_DATA,0x09); //IW4
-	OutU8(PIC1_DATA,0xFA); //Mask all but IRQ0 (timer) and IRQ2 Cascade.
-	OutU8(PIC2_DATA,0xFF);
+	OutU8(PIC_1,0x11); //IW1
+	OutU8(PIC_2,0x11); //IW1
+	OutU8(PIC_1_DATA,0x20); //IW2
+	OutU8(PIC_2_DATA,0x28); //IW2
+	OutU8(PIC_1_DATA,0x04); //IW3
+	OutU8(PIC_2_DATA,0x02); //IW3
+	OutU8(PIC_1_DATA,0x0D); //IW4
+	OutU8(PIC_2_DATA,0x09); //IW4
+	OutU8(PIC_1_DATA,0xFA); //Mask all but IRQ0 (timer) and IRQ2 Cascade.
+	OutU8(PIC_2_DATA,0xFF);
 }
 
 interrupt U0 IntNop()
 {//Make unplanned IRQs stop by all means!
-	OutU8(PIC2,PIC_EOI);
-	OutU8(PIC1,PIC_EOI);
+	OutU8(PIC_2,PIC_EOI);
+	OutU8(PIC_1,PIC_EOI);
 	*(dev.uncached_alias + LAPIC_EOI)(U32 *) = 0;
 }
 

src/Kernel/KMain.CC

@@ -106,8 +106,8 @@ U0 SysGrInit()
 U0 TimerInit()
 {//See $LK,"::/Doc/PIT.DD",A="FI:::/Doc/PIT.DD"$.
 	OutU8(PIT_CMD, PIT_CMDF_CHANNEL0 | PIT_CMDF_OPMODE_RATE_GEN | PIT_CMDF_ACCESS_WORD);
-	OutU8(PIT0,SYS_TIMER0_PERIOD);
-	OutU8(PIT0,SYS_TIMER0_PERIOD >> 8);
+	OutU8(PIT_0,SYS_TIMER0_PERIOD);
+	OutU8(PIT_0,SYS_TIMER0_PERIOD >> 8);
 }
 
 U0 Reboot(Bool format_ramdisks=FALSE)

src/Kernel/KMisc.CC

@@ -15,7 +15,7 @@ U0 IntCore0TimerHandler(CTask *)
 	LBtr(&sys_semas[SEMA_SYS_TIMER],0);
 	for (i=1;i<mp_count;i++)
 		MPInt(I_TIMER,i);
-	OutU8(PIC1,PIC_EOI); //Acknowledge PIC Interrupt
+	OutU8(PIC_1,PIC_EOI); //Acknowledge PIC Interrupt
 }
 
 I64 SysTimerRead()
@@ -27,9 +27,9 @@ I64 SysTimerRead()
 		while (LBts(&sys_semas[SEMA_SYS_TIMER],0))
 			PAUSE
 	OutU8(PIT_CMD, PIT_CMDF_CHANNEL0); //Latch Timer0
-	if ((i=InU8(PIT0) + InU8(PIT0) << 8) == SYS_TIMER0_PERIOD)
+	if ((i=InU8(PIT_0) + InU8(PIT_0) << 8) == SYS_TIMER0_PERIOD)
 	{
-		if (InU8(PIC1) & 1)
+		if (InU8(PIC_1) & 1)
 			i=-1;
 	}
 	res=counts.timer+SYS_TIMER0_PERIOD-i;
@@ -133,8 +133,8 @@ U0 Sound(I8 ona=0)
 			period=ClampI64(SYS_TIMER_FREQ/Ona2Freq(ona),1,U16_MAX);
 			//See $LK,"::/Doc/PIT.DD",A="FI:::/Doc/PIT.DD"$.
 			OutU8(PIT_CMD,PIT_CMDF_CHANNEL2 | PIT_CMDF_OPMODE_SQUARE_WAVE | PIT_CMDF_ACCESS_WORD);
-			OutU8(PIT2,period);
-			OutU8(PIT2,period.u8[1]);
+			OutU8(PIT_2,period);
+			OutU8(PIT_2,period.u8[1]);
 			OutU8(PCSPKR,3|InU8(PCSPKR)); //enable speaker
 		}
 		if (!IsDebugMode && screencast.record)

src/Kernel/KernelA.HH

@@ -309,30 +309,30 @@ public class CMathODE
 
 #help_index "Processor"
 //IDT entry types
-#define IDTET_TASK							0x05
-#define IDTET_IRQ 							0x0E
-#define IDTET_TRAP							0x0F //Same as IRQ but doesnt do CLI.
+#define IDTET_TASK		0x05
+#define IDTET_IRQ 		0x0E
+#define IDTET_TRAP		0x0F //Same as IRQ but doesnt do CLI.
 
 //Interrupts
 //0x00-0x1F are reserved by Intel
-#define I_DIV_ZERO							0x00
-#define I_SINGLE_STEP 					0x01
-#define I_NMI 									0x02
-#define I_BPT 									0x03
-#define I_PAGE_FAULT						0x0E
+#define I_DIV_ZERO		0x00
+#define I_SINGLE_STEP 	0x01
+#define I_NMI 			0x02
+#define I_BPT 			0x03
+#define I_PAGE_FAULT	0x0E
 //0x20-0x2F are used for hardware
-#define I_TIMER 								0x20
+#define I_TIMER 		0x20
 //Software Interrupts
-#define I_MP_CRASH							0x30
-#define I_WAKE									0x31
-#define I_DEBUG 								0x32
+#define I_MP_CRASH		0x30
+#define I_WAKE			0x31
+#define I_DEBUG 		0x32
 //See $LK,"ST_INT_NAMES",A="MN:ST_INT_NAMES"$
 
 //You might want to start backward from
 //0xFF for your own interrupts.
-#define I_USER									0x40
+#define I_USER			0x40
 
-#define MP_PROCESSORS_NUM 			128
+#define MP_PROCESSORS_NUM 	128
 
 //Control register flag bits
 #define CR0f_PE		0 //Protection Enable (Protected mode)
@@ -614,10 +614,10 @@ class CKernel
 #define IA32_GS_BASE		0xC0000101
 
 //Programmable Interrupt Controller
-#define PIC1						0x20
-#define PIC1_DATA 			0x21
-#define PIC2						0xA0
-#define PIC2_DATA 			0xA1
+#define PIC_1						0x20
+#define PIC_1_DATA 			0x21
+#define PIC_2						0xA0
+#define PIC_2_DATA 			0xA1
 #define PIC_EOI 				0x20 //End of interrupt
 
 //Local Advanced Programmable Interrupt Controller
@@ -669,8 +669,8 @@ class CAP16BitInit
 #help_index "Time/PIT"
 #help_file "::/Doc/PIT.DD"
 //Programmable Interval Timer
-#define PIT0		0x40
-#define PIT2		0x42
+#define PIT_0		0x40
+#define PIT_2		0x42
 #define PIT_CMD 0x43
 
 #define PIT_CMDF_OPMODE_RATE_GEN				0x04

src/Kernel/SerialDev/Keyboard.CC

@@ -408,7 +408,7 @@ U0 KbdPacketRead()
 interrupt U0 IRQKbd()
 {
 	CLD
-	OutU8(PIC1,PIC_EOI);
+	OutU8(PIC_1,PIC_EOI);
 	kbd.irqs_working=TRUE;
 	if (mouse_hard.install_in_progress) {
 		kbd.reset=TRUE;
@@ -432,7 +432,7 @@ U0 KbdInit()
 		Fs->catch_except=TRUE;
 	}
 	IntEntrySet(0x21,&IRQKbd);
-	OutU8(PIC1_DATA,InU8(PIC1_DATA)&~2);
+	OutU8(PIC_1_DATA,InU8(PIC_1_DATA)&~2);
 }
 
 U0 KbdHandler()

src/Kernel/SerialDev/Mouse.CC

@@ -90,8 +90,8 @@ U0 MouseHardPacketRead()
 interrupt U0 IRQMouseHard()
 {
 	CLD
-	OutU8(PIC2,PIC_EOI);
-	OutU8(PIC1,PIC_EOI);
+	OutU8(PIC_2,PIC_EOI);
+	OutU8(PIC_1,PIC_EOI);
 	mouse_hard.irqs_working=TRUE;
 	if (mouse_hard.install_in_progress || !mouse_hard.installed) {
 		kbd.reset=TRUE;
@@ -312,13 +312,13 @@ Bool MouseHardDriverInstall(I64 dummy=0) //can be spawned
 	no_warn dummy;
 	I64 i;
 	mouse_hard.install_in_progress=TRUE;
-	OutU8(PIC2_DATA,InU8(PIC2_DATA)|0x10);
+	OutU8(PIC_2_DATA,InU8(PIC_2_DATA)|0x10);
 	mouse_hard.installed=mouse_hard.irqs_working=FALSE;
 	IntEntrySet(0x2C,&IRQMouseHard);
 	for(i=0;i<5;i++)
 		mouse_hard.bttns[i]=0;
 	if (i=MouseHardReset)
-		OutU8(PIC2_DATA,InU8(PIC2_DATA)&~0x10);
+		OutU8(PIC_2_DATA,InU8(PIC_2_DATA)&~0x10);
 	KbdMouseReset;
 	mouse_hard.install_attempts++;
 	mouse_hard.installed=mouse_hard.event=i;

src/Misc/PCIDevices.DD

@@ -7158,7 +7158,7 @@
 				A009		CCSI PCI20-5-485 5 Mbit ARCnet
 				A00A		CCSI PCI20-5-485D 5 Mbit ARCnet
 				A00B		CCSI PCI20-5-485X 5 Mbit ARCnet
-				A00C		CCSI PIC20-5-FOG-ST 5 Mbit ARCnet
+				A00C		CCSI PIC_20-5-FOG-ST 5 Mbit ARCnet
 				A00D		CCSI PCI20-5-FOG-SMA 5 Mbit ARCnet
 				A00E		COM200C22 ARCNET
 				A201		CCSI PCI22-485 10 Mbit ARCnet