mirror of
https://github.com/Zeal-Operating-System/ZealOS.git
synced 2024-12-25 23:10:32 +00:00
Add comments to some compiler methods.
Revert 440Hz 'A' tuning.
This commit is contained in:
parent
1b2144c451
commit
2836d36ca6
14 changed files with 99 additions and 65 deletions
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@ -22,8 +22,6 @@ Features in development include:
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- Added comments and documentation
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- HolyC -> CosmiC
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- System-wide renaming for clarity
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- Removed shift-space mechanism
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- 440Hz 'A' tuning changed to 432Hz
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## Getting started
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@ -44,7 +42,7 @@ Afterwards, you can make a pull request on the `master` branch.
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## Background
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In around November of 2019, [VoidNV](https://web.archive.org/web/20210414181948/https://github.com/VoidNV) forked [ZenithOS](https://web.archive.org/web/20200811190005/https://github.com/VoidNV/ZenithOS) from TempleOS to continue Terry's work in a direction that would make it a viable operating system while still keeping the innovative and divine-intellect ideas and design strategies intact. At first, development occurred exclusively inside a VM and ISOs were occasionally generated as official releases, but this was scrapped and restarted from scratch. [Releases of the "old" ZenithOS are currently archived on the mega.nz website.](https://mega.nz/#F!ZIEGmSRQ!qvL6Wk6THzE-dazkfT6N3Q) The repository was removed in August of 2020, and reuploaded to [ZenithOS](https://web.archive.org/web/20210630230454/https://github.com/ZenithOS/ZenithOS). The latest archived [front page](https://web.archive.org/web/20200811190005/https://github.com/VoidNV/ZenithOS/), [master.zip](https://web.archive.org/web/20200811190054/https://codeload.github.com/VoidNV/ZenithOS/zip/master), and [related links](https://web.archive.org/web/*/https://github.com/VoidNV/ZenithOS/*) can be found on archive.org.
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In around November of 2019, [VoidNV](https://web.archive.org/web/20210414181948/https://github.com/VoidNV) forked [ZenithOS](https://web.archive.org/web/20200811190005/https://github.com/VoidNV/ZenithOS) from TempleOS. [Releases of pre-git ZenithOS are currently archived on the mega.nz website.](https://mega.nz/#F!ZIEGmSRQ!qvL6Wk6THzE-dazkfT6N3Q) The repository was removed in August of 2020, and reuploaded to [ZenithOS](https://web.archive.org/web/20210630230454/https://github.com/ZenithOS/ZenithOS). The latest archived [front page](https://web.archive.org/web/20200811190005/https://github.com/VoidNV/ZenithOS/), [master.zip](https://web.archive.org/web/20200811190054/https://codeload.github.com/VoidNV/ZenithOS/zip/master), and [related links](https://web.archive.org/web/*/https://github.com/VoidNV/ZenithOS/*) can be found on archive.org.
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In July of 2021, ZealOS was forked from ZenithOS.
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@ -219,7 +219,7 @@ U0 ICSub(CIntermediateCode *tmpi,
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if (!swap)
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{
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op = 0x03;
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ICU24(tmpi, 0xD8F748);
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ICU24(tmpi, 0xD8F748); // NEG RAX
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}
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i = ICModr1(REG_RAX, t2, r2, d2);
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if (tmpi->ic_flags & ICF_LOCK)
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@ -257,7 +257,7 @@ U0 ICSub(CIntermediateCode *tmpi,
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if (swap)
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{
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op = 0x03;
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ICU24(tmpi, 0xD9F748);
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ICU24(tmpi, 0xD9F748); // NEG U64 RCX
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}
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if (r3 > 7)
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i++;
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@ -379,11 +379,11 @@ U0 ICMulEqu(CIntermediateCode *tmpi, I64 rip)
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MDF_DISP + tmpi->arg1_type_pointed_to, REG_RCX, 0, rip);
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r = REG_RBX;
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if (I8_MIN <= i <= I8_MAX)
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ICU32(tmpi, i << 24 + 0xDB6B48);
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ICU32(tmpi, i << 24 + 0xDB6B48); // IMUL2 U64 RBX, I8 i
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else
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{
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ICU24(tmpi, 0xDB6948);
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ICU32(tmpi, i);
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ICU24(tmpi, 0xDB6948); //
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ICU32(tmpi, i); // IMUL2 U64 RBX, U32 i
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}
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ICMov(tmpi, MDF_DISP + tmpi->arg1_type_pointed_to, REG_RCX, 0, MDF_REG + RT_I64, REG_RBX, 0, rip);
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}
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@ -424,12 +424,12 @@ U0 ICDiv(CIntermediateCode *tmpi, I64 rip)
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if (tmpi->ic_class->raw_type & RTF_UNSIGNED)
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{
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ICZero(tmpi, REG_RDX);
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ICU24(tmpi, 0xF1F748);
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ICU24(tmpi, 0xF1F748); // DIV U64 RCX
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}
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else
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{
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ICU16(tmpi, 0x9948);
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ICU24(tmpi, 0xF9F748);
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ICU16(tmpi, 0x9948); // CQO
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ICU24(tmpi, 0xF9F748); // IDIV U64 RAX
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}
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ICMov(tmpi, tmpi->res.type, tmpi->res.reg, tmpi->res.disp, MDF_REG + RT_I64, REG_RAX, 0, rip);
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}
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@ -445,12 +445,12 @@ U0 ICDivEqu(CIntermediateCode *tmpi, Bool is_mod, I64 rip)
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if (tmpi->ic_class->raw_type & RTF_UNSIGNED)
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{
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ICZero(tmpi, REG_RDX);
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ICU24(tmpi, 0xF1F748);
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ICU24(tmpi, 0xF1F748); // DIV U64 RCX
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}
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else
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{
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ICU16(tmpi, 0x9948);
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ICU24(tmpi, 0xF9F748);
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ICU16(tmpi, 0x9948); // CQO
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ICU24(tmpi, 0xF9F748); // IDIV U64 RAX
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}
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if (is_mod)
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ICMov(tmpi, tmpi->arg1.type & MDG_MASK + tmpi->arg1_type_pointed_to,
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@ -468,12 +468,12 @@ U0 ICDivEqu(CIntermediateCode *tmpi, Bool is_mod, I64 rip)
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if (tmpi->ic_class->raw_type & RTF_UNSIGNED)
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{
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ICZero(tmpi, REG_RDX);
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ICU24(tmpi, 0xF1F748);
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ICU24(tmpi, 0xF1F748); // DIV U64 RCX
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}
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else
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{
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ICU16(tmpi, 0x9948);
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ICU24(tmpi, 0xF9F748);
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ICU16(tmpi, 0x9948); // CQO
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ICU24(tmpi, 0xF9F748); // IDIV U64 RAX
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}
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if (is_mod)
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ICMov(tmpi, MDF_DISP + tmpi->arg1_type_pointed_to, REG_RBX, 0, MDF_REG + RT_I64, REG_RDX, 0, rip);
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@ -496,12 +496,12 @@ U0 ICMod(CIntermediateCode *tmpi, I64 rip)
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if (tmpi->ic_class->raw_type & RTF_UNSIGNED)
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{
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ICZero(tmpi, REG_RDX);
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ICU24(tmpi, 0xF1F748);
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ICU24(tmpi, 0xF1F748); // DIV U64 RCX
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}
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else
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{
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ICU16(tmpi, 0x9948);
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ICU24(tmpi, 0xF9F748);
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ICU16(tmpi, 0x9948); // CQO
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ICU24(tmpi, 0xF9F748); // IDIV U64 RAX
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}
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ICMov(tmpi, tmpi->res.type, tmpi->res.reg, tmpi->res.disp, MDF_REG + RT_I64, REG_RDX, 0, rip);
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}
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done = TRUE;
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}
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else if (op.u8[2] == 0x24)
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{//AND
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{ // AND
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ICMov(tmpi, MDF_REG + RT_I64, REG_RCX, 0, t2, r2, d2, rip);
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ICMov(tmpi, MDF_REG + RT_I64, REG_RAX, 0, MDF_DISP + type_pointed_to, REG_RCX, 0, rip);
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res_reg = REG_RAX;
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done = TRUE;
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}
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else if (type_pointed_to < RT_I64)
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{//OR/XOR
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{ // OR/XOR
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ICMov(tmpi, MDF_REG + RT_I64, REG_RCX, 0, t2, r2, d2, rip);
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ICMov(tmpi, MDF_REG + RT_I64, REG_RAX, 0, MDF_DISP + type_pointed_to, REG_RCX, 0, rip);
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res_reg = REG_RAX;
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@ -13,7 +13,7 @@ U0 ICNot(CIntermediateCode *tmpi, I64 rip)
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{
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i = ICModr1(tmpi, tmpi->arg1.type, tmpi->arg1.reg, tmpi->arg1.disp);
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ICRex(tmpi, i.u8[1]);
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ICU16(tmpi, i.u8[2] << 8 + 0xF6); //TEST ?,0xFF
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ICU16(tmpi, i.u8[2] << 8 + 0xF6); // TEST ?, 0xFF
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ICModr2(tmpi, i,, tmpi->arg1.disp, rip + 1);
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ICU8(tmpi, 0xFF);
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}
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ICMov(tmpi, MDF_REG + RT_I64, REG_RAX, 0, tmpi->arg1.type, tmpi->arg1.reg, tmpi->arg1.disp, rip);
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ICTest(tmpi, REG_RAX);
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}
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ICU24(tmpi, 0xC0940F); //SETZ AL
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ICU32(tmpi, 0xC0B60F48);//MOVZX RAX,AL
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ICU24(tmpi, 0xC0940F); // SETE AL
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ICU32(tmpi, 0xC0B60F48);// MOVZX RAX, AL
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ICMov(tmpi, tmpi->res.type, tmpi->res.reg, tmpi->res.disp, MDF_REG + RT_U64, REG_RAX, 0, rip);
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}
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r2 = tmpi->arg1.reg;
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ICZero(tmpi, REG_RAX);
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ICTest(tmpi, r2);
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ICU16(tmpi, 0x0874);
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ICU16(tmpi, 0x0874); // JE I8 0xA
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ICTest(tmpi, REG_RCX);
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ICU16(tmpi, 0x0374);
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ICU24(tmpi, 0xC0FF48);
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ICU16(tmpi, 0x0374); // JE I8 0x5
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ICU24(tmpi, 0xC0FF48); // INC U64 RAX
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ICMov(tmpi, tmpi->res.type, tmpi->res.reg, tmpi->res.disp, MDF_REG + RT_I64, REG_RAX, 0, rip);
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}
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}
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ICZero(tmpi, REG_RAX);
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ICU24(tmpi, 0xC80B00 + i + r2 << 16);
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ICU16(tmpi, 0x0374);
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ICU24(tmpi, 0xC0FF48);
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ICU16(tmpi, 0x0374); // JE I8 0x5
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ICU24(tmpi, 0xC0FF48); // INC U64 RAX
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ICMov(tmpi, tmpi->res.type, tmpi->res.reg, tmpi->res.disp, MDF_REG + RT_I64, REG_RAX, 0, rip);
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}
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@ -87,15 +87,15 @@ U0 ICXorXor(CIntermediateCode *tmpi, I64 rip)
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r2 = tmpi->arg1.reg;
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ICZero(tmpi, REG_RBX);
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ICTest(tmpi, r2);
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ICU16(tmpi, 0x0374);
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ICU24(tmpi, 0xC3FF48);
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ICU16(tmpi, 0x0374); // JE I8 0x5
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ICU24(tmpi, 0xC3FF48); // INC U64 RBX
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ICZero(tmpi, REG_RAX);
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ICTest(tmpi, REG_RCX);
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ICU16(tmpi, 0x0374);
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ICU24(tmpi, 0xC0FF48);
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ICU16(tmpi, 0x0374); // JE I8 0x5
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ICU24(tmpi, 0xC0FF48); // INC U64 RAX
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ICU24(tmpi, 0xC33348);
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ICU24(tmpi, 0xC33348); // XOR U64 RAX, U64 RBX
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ICMov(tmpi, tmpi->res.type, tmpi->res.reg, tmpi->res.disp, MDF_REG + RT_I64, REG_RAX, 0, rip);
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}
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@ -173,7 +173,7 @@ U0 ICComp(CIntermediateCode *tmpi, I64 us, I64 is, I64 rip)
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if (tmpi->ic_class->raw_type & RTF_UNSIGNED || tmpi->ic_flags & ICF_USE_UNSIGNED)
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is = us;
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ICU16(tmpi, 0x300 + is);
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ICU24(tmpi, 0xC0FF48);
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ICU24(tmpi, 0xC0FF48); // INC U64 RAX
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ICMov(tmpi, tmpi->res.type, tmpi->res.reg, tmpi->res.disp, MDF_REG + RT_I64, REG_RAX, 0, rip);
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}
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else
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if (tmpi->ic_class->raw_type & RTF_UNSIGNED || tmpi->ic_flags & ICF_USE_UNSIGNED)
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is = us;
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ICU16(tmpi, 0x300 + is);
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ICU24(tmpi, 0xC0FF48);
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ICU24(tmpi, 0xC0FF48); // INC U64 RAX
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ICMov(tmpi, tmpi->res.type, tmpi->res.reg, tmpi->res.disp, MDF_REG + RT_I64, REG_RAX, 0, rip);
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}
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}
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@ -298,11 +298,11 @@ U0 ICBitOps(CIntermediateCode *tmpi, CICArg *arg1, CICArg *arg2, CIntermediateCo
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U0 ICToUpper(CIntermediateCode *tmpi, I64 rip)
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{
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ICMov(tmpi, MDF_REG + RT_I64, REG_RAX, 0, tmpi->arg1.type, tmpi->arg1.reg, tmpi->arg1.disp, rip);
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ICU32(tmpi, 0x61F88348);
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ICU16(tmpi, 0x0A7C);
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ICU32(tmpi, 0x7AF88348);
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ICU16(tmpi, 0x047F);
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ICU32(tmpi, 0xE0C08348);
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ICU32(tmpi, 0x61F88348); // CMP U64 RAX, I8 0x61
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ICU16(tmpi, 0x0A7C); // JL I8 0xC
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ICU32(tmpi, 0x7AF88348); // CMP U64 RAX, I8 0x7A
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ICU16(tmpi, 0x047F); // JG I8 0x6
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ICU32(tmpi, 0xE0C08348); // ADD U64 RAX, I8 0xE0
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}
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U0 ICToI64(CCompCtrl *cc, CIntermediateCode *tmpi, I64 rip)
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@ -327,8 +327,8 @@ U0 ICToBool(CCompCtrl *, CIntermediateCode *tmpi, I64 rip)
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r = REG_RAX;
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}
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ICTest(tmpi, r);
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ICU24(tmpi, 0xC0950F); //SETNZ AL
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ICU32(tmpi, 0xC0B60F48); //MOVZX RAX,AL
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ICU24(tmpi, 0xC0950F); // SETNE AL
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ICU32(tmpi, 0xC0B60F48); // MOVZX RAX, AL
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}
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U0 ICPreIncDec(CIntermediateCode *tmpi, I64 op, I64 rip)
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@ -863,7 +863,7 @@ U0 ICSwitch(CIntermediateCode *tmpi, I64 rip, Bool nobound, CCompCtrl *cc, U8 *b
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if (lb->flags & (CMF_I8_JMP_TABLE | CMF_U8_JMP_TABLE | CMF_I16_JMP_TABLE | CMF_U16_JMP_TABLE))
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{
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ICU16(tmpi, 0xC381); //ADD EBX,0x12345678
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ICU16(tmpi, 0xC381); // ADD EBX, 0x########
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if (buf && cc->flags & CCF_AOT_COMPILE)
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{
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tmpa = CAlloc(sizeof(CAOTAbsAddr));
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@ -886,12 +886,12 @@ U0 ICSwitch(CIntermediateCode *tmpi, I64 rip, Bool nobound, CCompCtrl *cc, U8 *b
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U0 ICLocalVarInit(CIntermediateCode *tmpi)
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{
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ICU24(tmpi, 0xC48B48);
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ICU16(tmpi, 0x5748);
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ICU24(tmpi, 0xF88B48);
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ICU24(tmpi, 0xC1C748);
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ICU24(tmpi, 0xC48B48); // MOV U64 RAX, U64 RSP
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ICU16(tmpi, 0x5748); // PUSH U64 RDI
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ICU24(tmpi, 0xF88B48); // MOV U64 RDI, U64 RAX
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ICU24(tmpi, 0xC1C748); // MOV U64 RCX, I32 0x########
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ICU32(tmpi, tmpi->ic_data);
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ICU16(tmpi, sys_var_init_val << 8 + 0xB0);
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ICU24(tmpi, 0xAA48F3);
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ICU16(tmpi, 0x5F48);
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ICU16(tmpi, sys_var_init_val << 8 + 0xB0); // MOV AL, sys_var_init_val
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ICU24(tmpi, 0xAA48F3); // REP_STOSB
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ICU16(tmpi, 0x5F48); // POP U64 RDI
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}
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@ -15,8 +15,8 @@ extern I64 LexExpression(CCompCtrl *cc);
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extern I64 LexCharGet(CCompCtrl *cc);
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extern CCodeMisc *OptLabelFwd(CCodeMisc *lb);
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extern CIntermediateCode *OptPass012(CCompCtrl *cc);
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extern U0 OptPass3(CCompCtrl *cc,COptReg *reg_offsets);
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extern U0 OptPass4(CCompCtrl *cc,COptReg *reg_offsets,I64 *_type);
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extern U0 OptPass3(CCompCtrl *cc, COptReg *reg_offsets);
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extern U0 OptPass4(CCompCtrl *cc, COptReg *reg_offsets, I64 *_type);
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extern U0 OptPass5(CCompCtrl *cc);
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extern U0 OptPass6(CCompCtrl *cc);
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extern I64 OptPass789A(CCompCtrl *cc, COptReg *reg_offsets, U8 *buf, CDebugInfo **_debug);
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@ -2,7 +2,7 @@
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class CInternalType
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{
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U8 type,size, name[8];
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U8 type, size, name[8];
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} internal_types_table[INTERNAL_TYPES_NUM] = {
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{RT_I0, 0, "I0i"},
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{RT_I0, 0, "I0"},
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@ -26,7 +26,7 @@ CMP_TEMPLATES::
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MOV RBX, RSP
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FLD U64 [RBX]
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FLD U64 8[RBX]
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@@20: FPREM
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@@20: FPREM
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FSTSW
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TEST AX, 0x400
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JNZ @@20
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@ -463,3 +463,26 @@ $TX,"Peter Gadwa",HTML="http://www.wired.com/magazine/2010/11/mf_ticketmaster/al
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$TX,"Ticketmaster",HTML="http://www.nytimes.com/1994/11/06/business/ticketmaster-s-mr-tough-guy.html?pagewanted=a"$
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$TX,"Tom Foley",HTML="http://web.gccaz.edu/~tfoley/perspage.html"$
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$TX,"Graphic Technologies",HTML="https://web.archive.org/web/20020811060541/http://www.graphic-technologies.com/"$
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||||
|
||||
|
||||
|
||||
|
||||
$SP,"<1>",BI=1$
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|