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Fix PCNet PR formatting.
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parent
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commit
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1 changed files with 10 additions and 6 deletions
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@ -23,7 +23,7 @@
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#define PCNET_DW_RDP 0x10
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#define PCNET_DW_RDP 0x10
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#define PCNET_DW_RAP 0x14
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#define PCNET_DW_RAP 0x14
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#define PCNET_DW_BDP 0x1c
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#define PCNET_DW_BDP 0x1C
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#define PCNET_DW_RESET 0x18 // reset reg location when card is in 32-bit mode
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#define PCNET_DW_RESET 0x18 // reset reg location when card is in 32-bit mode
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#define PCNET_BCR_MISC_CONFIG 2
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#define PCNET_BCR_MISC_CONFIG 2
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@ -215,16 +215,20 @@ U32 PCNetCSRRead(U32 csr)
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U0 PCNetAutoLinkSelect()
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U0 PCNetAutoLinkSelect()
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{
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{
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U32 bcr = PCNetCSRRead(PCNET_BCR_FULL_DUPLEX_CTRL);
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U32 bcr = PCNetCSRRead(PCNET_BCR_FULL_DUPLEX_CTRL);
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Bts(&bcr,PCNET_BCR_FULL_DUPLEX_CTRL_FDEN);
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Bts(&bcr,PCNET_BCR_FULL_DUPLEX_CTRL_AUIFD);
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Bts(&bcr, PCNET_BCR_FULL_DUPLEX_CTRL_FDEN);
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PCNetBCRWrite(PCNET_BCR_FULL_DUPLEX_CTRL,bcr);
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Bts(&bcr, PCNET_BCR_FULL_DUPLEX_CTRL_AUIFD);
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PCNetBCRWrite(PCNET_BCR_FULL_DUPLEX_CTRL, bcr);
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}
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}
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U0 PCNetEnableFullDuplex()
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U0 PCNetEnableFullDuplex()
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{
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{
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U32 bcr = PCNetCSRRead(PCNET_BCR_MISC_CONFIG);
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U32 bcr = PCNetCSRRead(PCNET_BCR_MISC_CONFIG);
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Bts(&bcr,PCNET_BCR_MISC_CONFIG_ASEL);
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PCNetBCRWrite(PCNET_BCR_MISC_CONFIG,bcr);
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Bts(&bcr, PCNET_BCR_MISC_CONFIG_ASEL);
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PCNetBCRWrite(PCNET_BCR_MISC_CONFIG, bcr);
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}
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}
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