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AHCI reset
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Void NV
parent
540818a34c
commit
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3 changed files with 20 additions and 153 deletions
BIN
Zenith-latest-2020-04-28-02_58_47.iso → Zenith-latest-2020-04-28-22_23_49.iso
Executable file → Normal file
BIN
Zenith-latest-2020-04-28-02_58_47.iso → Zenith-latest-2020-04-28-22_23_49.iso
Executable file → Normal file
Binary file not shown.
13
src/Home/MakeHome.CC
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13
src/Home/MakeHome.CC
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@ -0,0 +1,13 @@
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Cd(__DIR__);;
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//If these are not present in /Home, it uses the version in the root dir. You
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//can make your own, modified, version of these files in your /Home directory.
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#include "~/HomeLocalize"
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#include "/Zenith/Boot/MakeBoot"
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#include "/Zenith/Utils/MakeUtils"
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#include "~/HomeWrappers"
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MapFileLoad("::/Kernel/Kernel");
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MapFileLoad("::/Compiler/Compiler");
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#include "~/HomeKeyPlugIns"
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#include "~/HomeSys"
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Cd("..");;
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@ -2704,157 +2704,14 @@ class CPCIDev
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public class CATARep
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{
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CATARep *next;
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I64 num,type,base0,base1,unit,irq;
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I64 num,
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type,
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base0,
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base1,
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unit,
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irq;
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};
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//AHCI definitions
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#define AHCI_SIG_ATA 0x00000101
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#define AHCI_SIG_ATAPI 0xEB140101
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#define AHCI_SIG_SEMB 0xC33C0101 //Enclosure Management Bridge... rare to encounter in the wild
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#define AHCI_SIG_PM 0x96690101 //Port multiplier... not relevant to PC-type systems.
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#define AHCI_MAX_PORTS 32
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#define AHCI_PRDT_MAX_LEN 32
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#define AHCI_PRDT_BYTES_BITS 22
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#define AHCI_PRDT_BYTES (1 << 22)
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#define AHCI_GHCf_HBA_RESET 0
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#define AHCI_GHCf_INTERRUPT_ENABLE 1
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#define AHCI_GHCf_AHCI_ENABLE 31
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#define AHCI_CAPSEXTf_BOH 0
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#define AHCI_BOHCf_BOS 0
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#define AHCI_BOHCf_OOS 1
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#define AHCI_BOHCf_BB 4
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#define AHCI_CHDESCf_W 6
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#define AHCI_CHDESCf_W (1 << 6)
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#define AHCI_CFDESCf_C 7
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#define AHCI_CFDESCf_C (1 << 7)
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#define AHCI_PxCMDf_ST 0
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#define AHCI_PxCMDf_SUD 1
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#define AHCI_PxCMDf_POD 2
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#define AHCI_PxCMDf_FRE 4
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#define AHCI_PxCMDf_FR 14
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#define AHCI_PxCMDf_CR 15
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#define AHCI_PxCMDf_ATAPI 24
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#define AHCI_PxCMDF_ST (1 << 0)
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#define AHCI_PxCMDF_SUD (1 << 1)
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#define AHCI_PxCMDF_POD (1 << 2)
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#define AHCI_PxCMDF_FRE (1 << 4)
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#define AHCI_PxCMDF_FR (1 << 14)
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#define AHCI_PxCMDF_CR (1 << 15)
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#define AHCI_PxCMDF_ATAPI (1 << 24)
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#define AHCI_PxIEf_DP 5
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#define AHCI_PxIEf_TFE 30
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#define AHCI_PxIEF_DP (1 << 5)
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#define AHCI_PxIEF_TFE (1 << 30)
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#define AHCI_PxSCTLf_DET_INIT 1
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#define AHCI_PxSCTLF_DET_INIT (1 << 0)
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#define AHCI_PxSSTSF_DET_PRESENT 3
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class CAHCIPort
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{
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U32 cmd_list_base_addr,
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cmd_list_base_addr_upper,
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fis_base_addr,
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fis_base_addr_upper,
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interrupt_status,
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interrupt_enable,
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cmd,
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reserved,
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task_file_data,
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signature,
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sata_status,
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sata_ctrl,
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sata_error,
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sata_active,
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cmd_issue,
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sata_notif,
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fis_switch_ctrl,
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device_sleep;
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U8 reserved[40],
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vendor[16];
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};
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class CAHCIHba
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{
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U32 caps,
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ghc,
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interrupt_status,
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ports_implemented,
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version,
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ccc_ctrl,
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ccc_location,
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em_location,
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em_ctrl,
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caps_ext,
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bohc;
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U8 reserved[116],
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vendor[96];
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CAHCIPort ports[32];
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};
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#define FIS_TYPE_H2D 0x27
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class CFisH2D
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{//Host to Device
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U8 type,
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desc, //We are concerned with bit #7. 1=command, 0=control
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cmd,
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feature_low,
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lba0,
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lba1,
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lba2,
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device,
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lba3,
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lba4,
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lba5,
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feature_high;
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U16 count;
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U8 icc,
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ctrl;
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U32 reserved;
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};
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class CPrdtEntry
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{
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U32 data_base_addr,
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data_base_addr_upper,
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reserved,
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data_byte_count;
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};
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class CHBACmdHeader
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{
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U16 desc,
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prdt_len;
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U32 prdt_byte_count,
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cmd_table_base_addr,
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cmd_table_base_addr_upper,
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reserved[4];
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};
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class CHBACmdTable
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{
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U8 cmd_fis[64],
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acmd[16],
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reserved[48];
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CPrdtEntry prdt[8];
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};
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#define ATA_IDENT_SERIAL_NUM 10
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#define ATA_IDENT_MODEL_NUM 27
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#define ATA_IDENT_LBA48_CAPACITY 100
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//See $LK,"::/Doc/Credits.DD"$.
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#define ATA_NOP 0x00
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#define ATA_DEV_RST 0x08
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@ -3319,21 +3176,18 @@ public class CBlkDevGlobals
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boot_drive_let,
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first_hd_drive_let,
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first_dvd_drive_let;
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CAHCIHba *ahci_hba;
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CCacheBlk *cache_base,
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*cache_ctrl,
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**cache_hash_table;
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I64 cache_size,
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read_count,
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write_count,
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cmd_slot_count,
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mount_ide_auto_count,
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ins_base0,
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ins_base1; //Install cd/dvd controller.
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Bool dvd_boot_is_good,
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ins_unit,
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ahci64,
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pad[2];
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pad[3];
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};
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#help_index "File/Internal"
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