2021-07-03 05:07:57 +01:00
<!DOCTYPE HTML>
< html >
< head >
< meta http-equiv = "Content-Type" content = "text/html;charset=US-ASCII" >
2021-08-15 07:23:46 +01:00
< meta name = "generator" content = "ZealOS V0.16" >
2021-07-03 05:07:57 +01:00
< style type = "text/css" >
2021-07-29 03:20:15 +01:00
body {background-color:#fef1f0;}
.cF0{color:#000000;background-color:#fef1f0;}
.cF1{color:#0148a4;background-color:#fef1f0;}
.cF2{color:#3b7901;background-color:#fef1f0;}
.cF3{color:#057c7e;background-color:#fef1f0;}
.cF4{color:#bb2020;background-color:#fef1f0;}
.cF5{color:#9e42ae;background-color:#fef1f0;}
.cF6{color:#b57901;background-color:#fef1f0;}
.cF7{color:#b2b6af;background-color:#fef1f0;}
.cF8{color:#555753;background-color:#fef1f0;}
.cF9{color:#678fbb;background-color:#fef1f0;}
.cFA{color:#82bc49;background-color:#fef1f0;}
.cFB{color:#0097a2;background-color:#fef1f0;}
.cFC{color:#e26a6a;background-color:#fef1f0;}
.cFD{color:#c671bc;background-color:#fef1f0;}
.cFE{color:#c7ab00;background-color:#fef1f0;}
.cFF{color:#fef1f0;background-color:#fef1f0;}
2021-07-03 05:07:57 +01:00
< / style >
< / head >
< body >
2021-07-05 01:12:38 +01:00
< pre style = "font-family:monospace;font-size:12pt" >
2021-07-12 08:26:39 +01:00
< a name = "l1" > < / a > < span class = cF5 > 64-Bit Assembly Quiz< / span > < span class = cF0 >
2021-07-03 05:07:57 +01:00
< a name = "l2" > < / a >
< a name = "l3" > < / a > 1) In 64-bit mode, how many bytes are always pushed?
< a name = "l4" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l5" > < / a > PUSH 12
< a name = "l6" > < / a > PUSH EAX
2021-07-03 05:07:57 +01:00
< a name = "l7" > < / a >
< a name = "l8" > < / a > 2) What happens to the upper 32-bits?
< a name = "l9" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l10" > < / a > XOR EAX, EAX
< a name = "l11" > < / a > MOV EAX, 0x12345678
< a name = "l12" > < / a > MOV EAX, 0x80000000
2021-07-03 05:07:57 +01:00
< a name = "l13" > < / a >
< a name = "l14" > < / a > 3) How do you set FS or GS values?
< a name = "l15" > < / a >
< a name = "l16" > < / a > 4) If FS points to current task record, what's wrong with this instruction?
< a name = "l17" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l18" > < / a > MOV RAX, U64 FS:[TSS_SOME_MEMBER]
2021-07-03 05:07:57 +01:00
< a name = "l19" > < / a >
< a name = "l20" > < / a > 5) Which instruction takes more bytes?
< a name = "l21" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l22" > < / a > MOV RAX, U64 [R8]
< a name = "l23" > < / a > MOV RAX, U64 [R13]
2021-07-03 05:07:57 +01:00
< a name = "l24" > < / a >
< a name = "l25" > < / a > 6) Are these the same number of bytes?
< a name = "l26" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l27" > < / a > MOV RAX, 1234
< a name = "l28" > < / a > MOV R8, 1234
< a name = "l29" > < / a > MOV EAX, 1234
2021-07-03 05:07:57 +01:00
< a name = "l30" > < / a >
< a name = "l31" > < / a > 7) True or False
< a name = "l32" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l33" > < / a > a) You can access the lowest byte of RAX.
2021-07-03 05:07:57 +01:00
< a name = "l34" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l35" > < / a > b) You can access the lowest byte of ESI.
2021-07-03 05:07:57 +01:00
< a name = "l36" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l37" > < / a > c) You can access the second-to-lowest byte of RAX.
2021-07-03 05:07:57 +01:00
< a name = "l38" > < / a >
2021-07-04 23:11:34 +01:00
< a name = "l39" > < / a > d) You can access the second-to-lowest byte of ESI.
2021-07-03 05:07:57 +01:00
< a name = "l40" > < / a >
< a name = "l41" > < / a > 8) How do you call a subroutine at 0x10,0000,0000 from code at 0x00,0010,0000?
< a name = "l42" > < / a >
< a name = "l43" > < / a > 9) How much faster is a REL32 call instruction compared to a software interrupt or SYSCALL?
< a name = "l44" > < / a >
< a name = "l45" > < / a > 10) How long does an IN or OUT instruction take on a 1GHz machine and on a 3GHz machine?
< a name = "l46" > < / a >
< a name = "l47" > < / a > 11) How do you push all 16 regs?
< a name = "l48" > < / a >
< a name = "l49" > < / a > 12) Should you put the regs in a TSS?
< a name = "l50" > < / a >
< a name = "l51" > < / a > 13) You can have 4K or 4Meg pages in 32-bit mode. You can have 4K or what size pages in 64-bit mode?
< a name = "l52" > < / a >
< a name = "l53" > < / a > 14) On a fresh CPU with an empty TLB, how many memory accesses (page tables) does it take to access one virtual address?
< a name = "l54" > < / a >
< a name = "l55" > < / a > ----
< a name = "l56" > < / a >
2021-07-12 08:26:39 +01:00
< a name = "l57" > < / a > ZealOS identity-maps everything, all the time, so the usual convention of upper memory being for kernel does not apply. It
< a name = "l58" > < / a > uses physical addresses, basically. It puts all code in the lowest 2-Gig memory range so that it can use the CALL REL32
< a name = "l59" > < / a > instruction, the fastest. It never changes privilege levels or messes with page tables, once it is up-and-running.
2021-07-03 05:07:57 +01:00
< a name = "l60" > < / a >
< a name = "l61" > < / a > ----
< a name = "l62" > < / a >
< a name = "l63" > < / a > ANSWERS:
< a name = "l64" > < / a >
< a name = "l65" > < / a > 1) All stack pushes and pops are 64-bits.
< a name = "l66" > < / a >
< a name = "l67" > < / a > 2) The upper 32-bits are set to zero.
< a name = "l68" > < / a >
2021-07-26 20:29:49 +01:00
< a name = "l69" > < / a > 3) To set FS or GS, you use WRMSR to write a model specific reg. See < / span > < a href = "https://zeal-operating-system.github.io/ZealOS/Kernel/KernelA.HH.html#l626" > < span class = cF4 > IA32_FS_BASE< / span > < / a > < span class = cF0 > and < / span > < a href = "https://zeal-operating-system.github.io/ZealOS/Kernel/KUtils.CC.html#l536" > < span class = cF4 > SET_FS_BASE< / span > < / a > < span class = cF0 > .
2021-07-03 05:07:57 +01:00
< a name = "l70" > < / a >
< a name = "l71" > < / a > 4) Displacement addressing is now RIP relative, so RIP would be added to TSS_SOME_MEMBER. (Useless)
< a name = "l72" > < / a >
2021-07-26 20:29:49 +01:00
< a name = "l73" > < / a > 5) The R13 instruction takes one more byte because it is like < / span > < a href = "https://zeal-operating-system.github.io/ZealOS/Kernel/KernelA.HH.html#l1924" > < span class = cF4 > REG_RBP< / span > < / a > < span class = cF0 > in the ModR.
2021-07-03 05:07:57 +01:00
< a name = "l74" > < / a >
< a name = "l75" > < / a > 6) The R8 instruction needs a REX byte prefix to specify upper-8 reg.
< a name = "l76" > < / a >
< a name = "l77" > < / a > 7) You can access the lowest byte of any reg. You can access AH but not the second-to-lowest byte of ESI.
< a name = "l78" > < / a >
< a name = "l79" > < / a > 8) To call a subroutine farther than 2Gig away, you put the address into RAX, then CALL RAX.
< a name = "l80" > < / a >
2021-07-26 20:29:49 +01:00
< a name = "l81" > < / a > 9) CALL REL32 is significantly faster. See < / span > < a href = "https://zeal-operating-system.github.io/ZealOS/Demo/Lectures/InterruptDemo.CC.html#l1" > < span class = cF4 > ::/Demo/Lectures/InterruptDemo.CC< / span > < / a > < span class = cF0 > .
2021-07-03 05:07:57 +01:00
< a name = "l82" > < / a >
< a name = "l83" > < / a > 10) IN or OUT instructions happen at a fixed speed based on the original ISA bus clock.
< a name = "l84" > < / a >
< a name = "l85" > < / a > 11) PUSHAD is not available for 64-bit mode, so you do it by hand.
< a name = "l86" > < / a >
< a name = "l87" > < / a > 12) The TSS is no longer used to hold the task state because there are 16 regs and they are 64-bits, not 32-bits.
< a name = "l88" > < / a >
< a name = "l89" > < / a > 13) 64-bit mode has 4K or 2Meg page size.
< a name = "l90" > < / a >
< a name = "l91" > < / a > 14) For one access, there are 3-4 levels of page tables plus the location itself.
< / span > < / pre > < / body >
< / html >
