2022-08-20 00:54:34 +01:00
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#include <stdint.h>
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#include <stddef.h>
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#include <limine.h>
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2022-08-20 15:13:06 +01:00
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#include <lib.h>
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2022-08-20 00:54:34 +01:00
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2022-08-20 01:21:36 +01:00
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static volatile struct limine_module_request module_request = {
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.id = LIMINE_MODULE_REQUEST,
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.revision = 0
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};
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2022-08-20 15:13:06 +01:00
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static volatile struct limine_kernel_address_request kernel_address_request = {
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.id = LIMINE_KERNEL_ADDRESS_REQUEST,
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2022-08-20 00:54:34 +01:00
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.revision = 0
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};
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2022-08-20 15:13:06 +01:00
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static volatile struct limine_memmap_request memmap_request = {
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.id = LIMINE_MEMMAP_REQUEST,
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.revision = 0
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};
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#define MEM_E820_ENTRIES_NUM 48
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#define MEM_E820T_USABLE 1
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#define MEM_E820T_RESERVED 2
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#define MEM_E820T_ACPI 3
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#define MEM_E820T_ACPI_NVS 4
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#define MEM_E820T_BAD_MEM 5
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#define MEM_E820T_PERM_MEM 7
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struct CGDTEntry {
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uint64_t lo, hi;
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};
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#define MP_PROCESSORS_NUM 128
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struct CGDT {
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struct CGDTEntry null;
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struct CGDTEntry boot_ds;
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struct CGDTEntry boot_cs;
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struct CGDTEntry cs32;
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struct CGDTEntry cs64;
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struct CGDTEntry cs64_ring3;
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struct CGDTEntry ds;
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struct CGDTEntry ds_ring3;
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struct CGDTEntry tr[MP_PROCESSORS_NUM];
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struct CGDTEntry tr_ring3[MP_PROCESSORS_NUM];
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};
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2022-08-20 00:54:34 +01:00
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2022-08-20 14:05:23 +01:00
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struct CZXE {
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uint16_t jmp;
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uint8_t module_align_bits;
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uint8_t reserved;
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uint32_t signature;
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int64_t org;
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int64_t patch_table_offset;
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int64_t file_size;
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};
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2022-08-20 01:21:36 +01:00
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2022-08-20 14:37:16 +01:00
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struct CDate {
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uint32_t time;
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int32_t date;
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};
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struct CMemE820 {
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uint8_t *base;
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int64_t len;
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uint8_t type;
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uint8_t pad[3];
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};
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struct CSysLimitBase {
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uint16_t limit;
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uint8_t *base;
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};
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2022-08-20 14:05:23 +01:00
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struct CKernel {
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2022-08-20 15:13:06 +01:00
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struct CZXE h;
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2022-08-20 14:37:16 +01:00
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uint32_t jmp;
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uint32_t boot_src;
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uint32_t boot_blk;
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uint32_t boot_patch_table_base;
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uint32_t sys_run_level;
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struct CDate compile_time;
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2022-08-20 15:27:08 +01:00
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// U0 start
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2022-08-20 14:37:16 +01:00
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uint32_t boot_base;
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uint16_t mem_E801[2];
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2022-08-20 15:13:06 +01:00
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struct CMemE820 mem_E820[MEM_E820_ENTRIES_NUM];
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2022-08-20 14:37:16 +01:00
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uint64_t mem_physical_space;
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2022-08-20 15:13:06 +01:00
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struct {
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uint16_t limit;
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uint8_t *base;
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} __attribute__((packed)) sys_gdt_ptr;
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2022-08-20 14:37:16 +01:00
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uint16_t sys_pci_buses;
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2022-08-20 15:13:06 +01:00
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struct CGDT sys_gdt;
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uint32_t sys_font_ptr;
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} __attribute__((packed));
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#define BOOT_SRC_RAM 2
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#define RLF_16BIT 0b01
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#define RLF_VESA 0b10
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2022-08-20 01:21:36 +01:00
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2022-08-20 15:13:06 +01:00
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void lower(void);
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2022-08-20 14:37:16 +01:00
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2022-08-20 15:13:06 +01:00
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struct E801 {
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size_t lowermem;
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size_t uppermem;
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2022-08-20 01:21:36 +01:00
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};
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2022-08-20 15:13:06 +01:00
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struct E801 get_E801(void) {
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struct E801 E801 = {0};
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for (size_t i = 0; i < memmap_request.response->entry_count; i++) {
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struct limine_memmap_entry *entry = memmap_request.response->entries[i];
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if (entry->type == LIMINE_MEMMAP_USABLE) {
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if (entry->base == 0x100000) {
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if (entry->length > 0xf00000) {
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E801.lowermem = 0x3c00;
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} else {
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E801.lowermem = entry->length / 1024;
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}
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}
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if (entry->base <= 0x1000000 && entry->base + entry->length > 0x1000000) {
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E801.uppermem = ((entry->length - (0x1000000 - entry->base)) / 1024) / 64;
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}
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}
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2022-08-20 00:54:34 +01:00
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}
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2022-08-20 15:13:06 +01:00
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return E801;
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}
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2022-08-20 00:54:34 +01:00
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2022-08-20 15:13:06 +01:00
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void _start(void) {
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2022-08-20 01:21:36 +01:00
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struct limine_file *kernel = module_request.response->modules[0];
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2022-08-20 15:13:06 +01:00
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struct CKernel *CKernel = (void *)0x7c00;
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memcpy(CKernel, kernel->address, kernel->size);
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void *CORE0_32BIT_INIT;
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for (uint64_t *p = (uint64_t *)CKernel; ; p++) {
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if (*p != 0xaa23c08ed10bd4d7) {
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continue;
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}
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p++;
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if (*p != 0xf6ceba7d4b74179a) {
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continue;
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}
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p++;
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CORE0_32BIT_INIT = p;
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break;
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}
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CKernel->boot_src = BOOT_SRC_RAM;
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CKernel->boot_blk = 0;
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CKernel->boot_patch_table_base = (uintptr_t)CKernel + CKernel->h.patch_table_offset;
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CKernel->sys_run_level = RLF_VESA | RLF_16BIT;
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CKernel->boot_base = (uintptr_t)&CKernel->jmp;
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CKernel->sys_gdt.boot_ds.lo = 0x000093000000ffff;
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CKernel->sys_gdt.boot_cs.lo = 0x00009a000000ffff;
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CKernel->sys_gdt.cs32.lo = 0x00cf9a000000ffff;
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CKernel->sys_gdt.cs64.lo = 0x00af9b000000ffff;
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CKernel->sys_gdt.cs64_ring3.lo = 0x00affb000000ffff;
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CKernel->sys_gdt.ds.lo = 0x00af93000000ffff;
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CKernel->sys_gdt.ds_ring3.lo = 0x00aff3000000ffff;
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CKernel->sys_gdt_ptr.limit = sizeof(CKernel->sys_gdt) - 1;
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CKernel->sys_gdt_ptr.base = (void *)&CKernel->sys_gdt;
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struct E801 E801 = get_E801();
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CKernel->mem_E801[0] = E801.lowermem;
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CKernel->mem_E801[1] = E801.uppermem;
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for (size_t i = 0; i < memmap_request.response->entry_count; i++) {
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struct limine_memmap_entry *entry = memmap_request.response->entries[i];
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int our_type;
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switch (entry->type) {
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case LIMINE_MEMMAP_BOOTLOADER_RECLAIMABLE:
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case LIMINE_MEMMAP_KERNEL_AND_MODULES:
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case LIMINE_MEMMAP_USABLE:
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our_type = MEM_E820T_USABLE; break;
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case LIMINE_MEMMAP_ACPI_RECLAIMABLE:
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our_type = MEM_E820T_ACPI; break;
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case LIMINE_MEMMAP_ACPI_NVS:
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our_type = MEM_E820T_ACPI_NVS; break;
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case LIMINE_MEMMAP_BAD_MEMORY:
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our_type = MEM_E820T_BAD_MEM; break;
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case LIMINE_MEMMAP_RESERVED:
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default:
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our_type = MEM_E820T_RESERVED; break;
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}
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CKernel->mem_E820[i].base = (void *)entry->base;
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CKernel->mem_E820[i].len = entry->length;
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CKernel->mem_E820[i].type = our_type;
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}
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2022-08-20 14:06:55 +01:00
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2022-08-20 15:13:06 +01:00
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void *target_addr = (void *)lower - kernel_address_request.response->virtual_base;
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target_addr += kernel_address_request.response->physical_base;
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2022-08-20 14:06:55 +01:00
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2022-08-20 15:13:06 +01:00
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asm volatile ("jmp *%0" :: "a"(target_addr), "b"(CORE0_32BIT_INIT), "c"(&CKernel->sys_gdt_ptr) : "memory");
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2022-08-20 01:21:36 +01:00
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2022-08-20 15:13:06 +01:00
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__builtin_unreachable();
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2022-08-20 00:54:34 +01:00
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}
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